1
Characteristics subject to change without notice
2048 2.4. 3/1/01
SMS24
SUMMIT
MICROELECTRONICS, Inc.
SUMMIT MICROELECTRONICS, Inc., 2001 300 Orchard City Dr., Suite 131 Campbell, CA 95008 Phone 408-378-6461 FAX 408-378-6586 www.summitmicro.com
l
User Programmable Device Configuration
l
Guaranteed Reset Valid to VCC = 1V
l
Immune to Short Negative VCC Transients
l
Six Unique Pin Configurations
l
User Programmable Feature Options:
w
Reset Threshold Voltages
w
Reset Pulse Widths
w
Programmable Watchdog Timeouts
w
Programmable Over- or Under-Voltage Sens-
ing
l
High Reliability
w
Endurance: 100,000 erase/write cycles
w
Data retention: 100 years
Highly Programmble Voltage Supervisory Circuit
FEATURES
DEVICE TYPES
INTRODUCTION
The SMS24 is a configurable and in-system program-
mable second generation 8 pin supervisory circuit. This
single device is adaptable to provide the optimum func-
tionality for a given system or sub-system. User program-
mable functions available -- reset pulse width, watchdog
delays, and voltage monitor thresholds -- eliminate exter-
nal components and allow standardization to enhance
system reliability. Additionally, 4K bits of general purpose
EEPROM is available on all configurations. The SMS24
is available in six pin configurations, and is compatible with
all Summit programmable devices and other I2C compo-
nents.
Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from Sum-
mit Microelectronics.
2048 DTTable 2.1
NC
RESET#
NC
GND
V
CC
RESET
SCL
SDA
Device
Code
001
NC
RESET#
NC
GND
V
CC
WP
SCL
SDA
Device
Code
010
WDI
RESET#
NC
GND
V
CC
RESET
SCL
SDA
Device
Code
011
RESET#2
RESET#1
V
SENSE
GND
V
CC
MR#
SCL
SDA
Device
Code
100
V
LOW
#
RESET#
V
SENSE
GND
V
CC
RESET
SCL
SDA
Device
Code
101
V
LOW
#
RESET#
V
SENSE
GND
V
CC
WDI
SCL
SDA
Device
Code
110
2046 DT 1.0
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1
1
0
0
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0
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1
1
2
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
FUNCTIONAL BLOCK DIAGRAMS
Block Diagram Device Code 010
Block Diagram Device Code 001
+
GND
VCC
8
4
VTRIP
RESET
CONTROL
1.25V
SCL
6
SDA
5
2046 BD001 2.1
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
RESET#
2
RESET
7
PROGRAMMABLE
RESET PULSE
GENERATOR
PROGRAMMABLE
WATCHDOG
TIMER
+
GND
VCC
8
4
RESET#
2
VTRIP
RESET
CONTROL
WP
7
1.25V
SCL
6
SDA
5
2046 BD010 2.1
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
PROGRAMMABLE
WATCHDOG
TIMER
3
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
Block Diagram Device Code 100
Block Diagram Device Code 011
+
GND
VCC
8
4
RESET#
2
VTRIP
RESET
CONTROL
RESET
7
1.25V
SCL
6
SDA
5
2046 BD011 1.0
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
WDI
1
PROGRAMMABLE
WATCHDOG
TIMER
+
GND
VCC
8
4
RESET#1
2
VTRIP
RESET
CONTROL
MR#
1.25V
SCL
6
SDA
5
2046 BD100 1.1
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
VSENSE 3
1
+
RESET#2
7
PROGRAMMABLE
WATCHDOG
TIMER
4
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
Block Diagram Device Code 110
Block Diagram Device Code 101
+
GND
VCC
8
4
RESET#
2
VTRIP
RESET
CONTROL
RESET
7
1.25V
SCL
6
SDA
5
2046 BD101 1.0
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
VSENSE 3
VLOW#
1
PROGRAMMABLE
WATCHDOG
TIMER
+
OV
UV
+
GND
VCC
8
4
RESET#
2
VTRIP
RESET
CONTROL
WDI
7
1.25V
SCL
6
SDA
5
2046 BD110 1.0
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
VSENSE 3
VLOW#
1
PROGRAMMABLE
WATCHDOG
TIMER
+
OV
UV
5
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
*COMMENT
Stresses listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias ....................... -55C to 125C
Storage Temperature ............................ -65C to 150C
Lead Solder Temperature (10 secs) ................... 300 C
Terminal Voltage with Respect to GND:
V
CC
................................. -0.3V to 6.0V
All Others ........................ -0.3V to 6.0V
DC OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
(Over Recommended Operating Conditions; Voltages are relative to GND)
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2046 DCElect Table 2.0
RECOMMENDED OPERATING CONDITIONS
Temperature
40
C to 85
C.
Voltage
2.7V to 5.5V
ENDURANCE AND DATA RETENTION
The SMS24 is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
6
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
PIN DESCRIPTIONS
RESET#
This signal is an active-low open drain I/O. Whenever the
voltage on V
CC
is below the programmed threshold volt-
age the RESET# pin will be driven low. After V
CC
passes
through the threshold (in a positive direction) the RESET#
output will continue to be driven for the programmed time-
out period (t
PTO
). In most configurations RESET# is also
an input. Whenever it is driven low it will activate the reset
timer. The RESET# output will then be driven low by the
device for the programmed period. If the input pulse is of
shorter duration than t
PTO
, RESET# will continue to be
driven. If it is longer than t
PTO
, RESET# will be released
and follow the input back high.
RESET
This signal is an active-high open drain I/O. Whenever the
voltage on V
CC
is below the programmed threshold volt-
age the RESET pin will be driven high. After V
CC
passes
through the threshold (in a positive direction) the RESET
output will continue to be driven for the programmed time-
out period. In all configurations using RESET it is also an
input. Whenever it is driven high it will activate the reset
timer. The RESET output will then be driven high by the
device for the programmed period. If the input pulse is of
shorter duration than t
PTO
, RESET will continue to be
driven. If it is longer than t
PTO
, RESET will be released and
follow the input back low.
RESET#1 & RESET#2
These signals are active-low open drain outputs (not I/Os).
These outputs are only available to Device Code 100, and
are both set to a low state by any one of three events: V
CC
below trip level, V
SENSE
< 1.25V, or MR# strobed low.
MR#
Manual Reset input is an active low input. Whenever it is
taken low it will generate a reset time-out.
V
SENSE
This is a second voltage sense input connected to its own
comparator that has reference of 1.25V. The comparator
can be programmed to activate the V
LOW
# output either for
an over-voltage or under-voltage condition.
V
LOW
#
This is an active-low open-drain output that can be wire-
ORed with the RESET# output or tied directly to an
interrupt input.
WDI
This is the Watchdog Interrupt input. Whenever a transi-
tion occurs on WDI the watchdog timer will be cleared. If
the device does not receive an interrupt before t
WDTO
the
device will drive the reset output(s). The period t
WDTO
is
programmable for four basic values. It can also be placed
into an idle mode, facilitating system debug, and allowing
a system time to configure itself after a power-on.
WP
This is an auxilliary Write lockout input pin. When held high
no writes will occur.
SCL
The serial interface clock input.
SDA
The serial interface data I/O.
7
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
DEVICE OPERATION
REGISTERS
Configuration Register
The configuration Register, located at address 00, is
illustrated in Table 1. The Configuration Bits (6, 5, & 4)
select the basic Device Code, and are referred to as Con2,
Con1, and Con0. Bit 7 is the Lock Bit, and when set to 1
locks the contents of the register.
Programming Registers
Once the device has been configured it is a simple matter
of writing to the two Programming Registers to prepare the
device for operation.
Note: The Threshold Trim* Bits are set at the
factory. Before modifying them you must read the
contents and save the value so that it can be
written back into the device. After configuring
them Bit 7 should be set to a 1 to prevent inadvert-
ent modification.
Table 1. Configuration Register
B
S
M
7
6
5
4
3
2
1
B
S
L
0
K
C
O
L
2
n
o
C
1
n
o
C
0
n
o
C
3
T
2
T
1
T
0
T
x
s
e
d
o
C
e
c
i
v
e
D
d
il
a
V
m
i
r
T
d
l
o
h
s
e
r
h
T
*
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
0
n
e
p
O
r
e
t
s
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e
R
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t
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f
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o
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1
)
e
li
t
a
l
o
v
-
n
o
n
(
d
e
k
c
o
L
n
o
i
t
a
r
u
g
i
f
n
o
C
Table 2. Programming Register 0
B
S
M
7
6
5
4
3
2
1
B
S
L
0
x
1
T
R
0
T
R
4
R
R
3
R
R
2
R
R
1
R
R
0
R
R
s
t
l
o
V
d
l
o
h
s
e
r
h
T
t
e
s
e
R
s
t
i
B
d
l
o
h
s
e
r
h
T
t
e
s
e
R
V
5
1
.
2
0
0
0
0
1
V
5
6
.
2
0
0
0
1
0
V
0
9
.
2
0
0
1
0
0
V
5
7
3
.
4
0
1
0
0
0
V
5
2
6
.
4
1
0
0
0
0
s
t
i
B
t
u
o
e
m
i
T
t
e
s
e
R
s
d
n
o
c
e
S
t
u
o
e
m
i
T
t
e
s
e
R
0
0
s
m
5
2
0
1
s
m
0
5
1
0
s
m
0
0
1
1
1
s
m
0
0
2
2046 Table01 2.0
2046 Table02 2.0
8
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
MEMORY OPERATION
The SMS24 memory is configured as a 2K x 8 array. Data
is received and transmitted via an industry standard two-
wire interface. The bus was designed for two-way, two-
line serial communication between different integrated
circuits. The two lines are a serial data line (SDA), and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus
Input Data Protocol
Configuring and programming the SMS24 is done using
the 2-wire serial interface. The device type address for this
operation is 1001
BIN
.
The protocol defines any device that sends data onto the
bus as a "transmitter" and any device that receives data as
a "re ceiver." The device controlling data transmission is
called the "master" and the controlled device is called the
"slave." In all cases the SMS24 will be a "slave" device,
since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as a start or a stop condition.
Table 3. Programming Register 1
B
S
M
7
6
5
4
3
2
1
B
S
L
0
x
K
C
O
L
V
O
d
d
A
T
D
2
D
W
1
D
W
0
D
W
s
d
n
o
c
e
S
t
u
o
e
m
i
T
g
o
d
h
c
t
a
W
s
t
i
B
t
u
o
e
m
i
T
g
o
d
h
c
t
a
W
e
d
o
M
e
l
d
I
r
o
F
F
O
0
0
x
s
4
.
0
0
1
1
s
8
.
0
1
0
0
s
6
.
1
1
0
1
s
2
.
3
1
1
0
s
4
.
6
1
1
1
x
x
x
0
D
e
c
i
v
e
T
0
1
0
1
s
s
e
r
d
d
A
e
p
y
1
D
e
c
i
v
e
T
1
1
0
1
s
s
e
r
d
d
A
e
p
y
0
o
t
s
d
n
o
p
s
e
R
d
d
A
s
a
i
B
n
i
P
s
s
e
r
x
1
s
e
r
o
n
g
I
d
d
A
s
a
i
B
n
i
P
s
s
e
r
0
V
E
S
N
E
S
)
V
5
2
.
1
(
d
l
o
h
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e
r
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T
>
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r
e
g
g
i
r
T
x
1
V
E
S
N
E
S
)
V
5
2
.
1
(
d
l
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h
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e
r
h
T
<
s
r
e
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g
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r
T
0
s
r
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t
s
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R
R
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t
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r
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o
2048 Table03 2.0
START and STOP Conditions
When both the data and clock lines are high, the bus is said
to be not busy. A high-to-low transition on the data line,
while the clock is high is defined as the "START" condition.
A low-to-high transition on the data line while the clock is
high is defined as the "STOP" condition.
Figure 1. START and STOP Conditions
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle the receiver will
pull the SDA line low to ACKnowledge that it received the
eight bits of data.
2046 Fig01 2.0
SCL
SDA In
START
Condition
STOP
Condition
9
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
The SMS24 will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected
the SMS24 will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word. In the READ mode
the SMS24 transmits eight bits of data, then releases the
SDA line, and monitors the line for an ACKnowledge
signal. If an ACKnowledge is detected, and if no STOP
condition is generated by the master, the SMS24 will
continue to transmit data. If an ACKnowledge is not
detected the SMS24 will terminate further data transmis-
sions and await a STOP condition before returning to the
standby power mode.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
Figure 2. Programming the SMS24
Write Configuration Register
Master
SDA
S
T
A
R
T
A
C
K
X X X
R
/
W
A
C
K
C
2
C
1
C
0
T
3
T
2
T
1
T
0
A
C
K
S
T
O
P
1
0
1 0
Master
SDA
Device Type
Address
Bus
Address
0 0 0 0 0 0 1 1
2046 Fig02 2.0
L
O
C
K
Program Register 0
S
T
A
R
T
A
C
K
X X X
R
/
W
A
C
K
A
C
K
S
T
O
P
1
0
1 0
Device Type
Address
Bus
Address
0 0 0 0 0 0 0 0
X
R
T
1
R
T
0
R
R
4
R
R
3
R
R
2
R
R
1
R
R
0
Program Register 1
S
T
A
R
T
A
C
K
X X X
R
/
W
A
C
K
A
C
K
S
T
O
P
1
0
1 0
Device Type
Address
Bus
Address
0 0 0 0 0 0 0 1
O
V
A
D
D
T
W
D
2
W
D
1
W
D
0
L
O
C
K
X
SMS24
SMS24
four bits of the slave address are the device type identifier.
For the SMS24 this is be 1010
BIN
or 1011
BIN
depending
upon the DT bit of PR1. The configuration and Program
Registers have a device type address of 1001.
The next three bits are the high order address bits.
The last bit of the data stream defines the operation to be
performed. When set to "1" a read operation is selected.
When set to "0" a write operation is selected.
WRITE OPERATIONS
The SMS24 allows two types of write operations: byte
write and page write. A byte write operation writes a single
byte during the nonvolatile write period (tWR). The page
write operation allows up to 16 bytes in the same page to
be written during tWR.
10
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
Table 4. Device Addressing
s
t
i
B
r
e
i
f
i
t
n
e
d
I
e
c
i
v
e
D
s
s
e
r
d
d
A
y
r
o
m
e
M
W
/
R
0
1
A
9
A
8
A
d
a
e
R
1
e
t
i
r
W
0
x
x
x
x
1
0
1
0
e
c
i
v
e
D
y
r
o
m
e
M
t
l
u
a
f
e
D
1
0
1
1
y
r
o
m
e
M
e
t
a
n
r
e
t
l
A
e
c
i
v
e
D
1
0
0
1
r
e
t
s
i
g
e
R
n
o
i
t
a
r
u
g
i
f
n
o
C
e
c
i
v
e
D
Byte Write
After the slave address is sent an ACKnowledge is gener-
ated and then the balance of the address is transmitted.
Upon receipt of the word address the SMS24 responds
with an ACKnowledge. After receiving the next byte of
data it again responds with an ACKnowledge. The master
then terminates the transfer by generating a STOP condi-
tion, at which time the SMS24 begins the internal write
cycle. While the internal write cycle is in progress the
SMS24 inputs are disabled and the device will not respond
to any requests from the master.
Page Write
The SMS24 is capable of a 16-byte page write operation.
It is initiated in the same manner as the byte-write opera-
tion, but instead of terminating the write cycle after the first
data word, the master can transmit up to 15 more bytes of
data. After the receipt of each byte the SMS24 will respond
with an ACKnowledge. The SMS24 automatically incre-
ments the address for subsequent data words. After the
receipt of each word the low order address bits are
internally incremented by one. The high order bits of the
address byte remain constant. Should the master transmit
more than 16 bytes, prior to generating the STOP condi-
tion, the address counter will rollover, and the previously
written data will be overwritten. As with the byte-write
operation all inputs are disabled during the internal write
cycle.
Acknowledge Polling
When the SMS24 is performing an internal WRITE opera-
tion it will ignore any new START conditions. Since the
device will only return an acknowledge after it accepts the
START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete. See the flow diagram for the proper
sequence of operations for polling.
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to "1." There are two different read
options: 1. Current Address Byte Read, or 2. Random
Address Byte Read
Current Address Read
The SMS24 contains an internal address counter which
maintains the address of the last word accessed, incre-
mented by one. If the last address accessed (either a read
or write) was to address location n, the next read operation
would access data from address location n+1 and incre-
2046 Table04 2.0
Next
Operation
a Write?
ACK
Returned
Issue
Address
Proceed
With
Write
Await
Next
Command
Issue Stop
Issue Slave
Address and
R/W = 0
Issue Stop
Write Cycle
In Progress
Yes
No
Issue Start
2046 Flow01 1.0
Yes
No
Flow Diagram
11
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
ment the current address pointer. When the SMS24
receives the slave address field with the R/W bit set to "1"
it issues an acknowledge and transmits the 8-bit word
stored at address location n+1. The current address byte
read operation only accesses a single byte of data. The
master does not acknowledge the transfer, but does
generate a stop condition. At this point the SMS24
discontinues data transmission.
Random Address Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condition
and the slave address field (with the R/W bit set to WRITE)
followed by the address of the word it is to read. This
procedure sets the internal address counter of the SMS24
to the desired address. After the word address
acknowlthe R/W bit set to READ. The SMS24 will respond
with an acknowledge and then transmit the 8-data bits
stored at the addressed location. At this point the master
does not acknowledge the transmission but does gener-
ate the stop condition. The SMS24 discontinues data
transmission and reverts to its standby power mode.
Sequential READ
Sequential reads can be initiated as either a current
address READ or random access READ. The first word
is transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowl-
edge, indicating that it requires additional data from the
SMS24. The SMS24 continues to output data for each
ACKnowledge received. The master terminates the se-
quential READ operation by not responding with an AC-
Knowledge, and issues a STOP condition. During a
sequential read operation the internal address counter is
automatically incremented with each ACKnowledge sig-
nal. For read operations all address bits are incremented,
allowing the entire array to be read using a single read
command. After a count of the last memory address the
address counter will rollover and the memory will continue
to output data.
12
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
IN-SYSTEM PROGRAMMING THE SMS24
The need for an in-system programming interface for a
supervisory circuit is necessitated by the rapid change to
both board designs (feature upgrades to a common de-
sign core) and the ICs resident on the boards. The SMS24
provides an ideal solution for maintaining currency with
the change in boards and their power supplies as they shift
from generation to generation.
Theory of Operation
The SMS24 can be designed-in with the simple addition of
an inexpensive 9-pin 0.100" centerline header. Summit
supports this configuration with the SMX3199-A program-
mer, and in the future will support this interface with the
SMX3200. Depending upon the end use of the interface,
prototyping vs. field support, the header can be placed
anywhere on the board or as a right angle header at the
back edge of the card (the side pointing outwards from a
card cage).
The basic interface circuit is shown in Figure 3. In order
to clearly illustrate the examples, all additional traces and
series resistors are either bold or outlined in a dashed box.
Notes:
If the device appears to be ignoring attempts to be
programmed ensure the supplied V
CC
is above the
programmed threshold. If V
CC
is below the reset
threshold all attempts to write to the device will be
ignored.
If you are writing to the memory array and `read-
backs' show occasional rows not being written check
the watchdog timer. Either disable the watchdog or
insure WDI is being strobed (high to low) at intervals
less than the programmed watchdog time out period.
Figure 3 is a block diagram illustration of the SMS24
configured as device code 110. The comments in bold
italics indicate the programmable options for this code
Supporting the SMS24 is a programming module, the
SMX3199-A. The hardware is a small printed circuit card
that interfaces to a standard PC parallel printer port. A
target programming cable is connected from this to the
user's card. The software provides an intuitive configura-
tion screen and also a memory test verification screen
(examples of the screens are shown).
SCL
SDA
VLOW#
VCC
WDI
RST#
VSENSE
GND
Device code 110
WDI
SCL
SDA
Board WDI in
Board Serial Bus
1k
1k
10k
10k
100k
1k
2046 Fig03 2.0
Board
RST#
Board
VSENSEIN
Figure 3. Basic Interface Circuit
13
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
+
GND
VCC
8
4
RESET#
2
VTRIP
RESET
CONTROL
WDI
7
1.25V
SCL
6
SDA
5
2046 Fig04 2.0
WRITE
CONTROL
NONVOLATILE
MEMORY
ARRAY
PROGRAMMABLE
RESET PULSE
GENERATOR
VSENSE 3
VLOW#
1
PROGRAMMABLE
WATCHDOG
TIMER
+
OV
UV
Programmable
Threshold
4.63V
4.37V
2.90V
2.65V
2.15V
Programmable
Device Type
Identifier
1010
1011
Programmable
Reset Pulse
25ms
50ms
100ms
200ms
Programmable
Watchdog Timer
Off
0.4s
0.8s
1.6s
3.2s
Programmable
VLOW Trigger
Overvoltage
Undervoltage
Figure 4. Programmable Options for Device Code 110
Figure 5. Configuration Screen
Figure 6. Memory Test Screen
14
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
Table 5. Memory AC Operating Characteristics
Figure 7. Memory Operating Characteristics
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2046 Fig07 2.0
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:
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(
w
o
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3
.
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s
t
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e
m
i
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s
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t
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s
n
t
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D
:
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m
i
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p
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n
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a
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a
D
0
5
2
s
n
t
T
A
D
:
D
H
e
m
i
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o
h
n
I
a
t
a
D
0
s
n
I
T
A
D
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d
n
a
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C
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r
e
t
li
f
e
s
i
o
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n
o
i
s
s
e
r
p
p
u
s
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s
i
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0
0
1
s
n
t
R
W
e
m
i
t
e
l
c
y
c
e
t
i
r
W
5
s
m
15
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
Figure 8. System Timing Patterns
V
PRST
V
CC
1V
RESET#
t
PTO
t
GLITCH
t
RPD
t
PTO
V
T
V
SENSE
1V
V
LOW
#
<t
GLITCH
t
RPD
t
RPD
t
RPD
V
T
V
SENSE
1V
V
LOW
#
<t
GLITCH
t
RPD
t
RPD
V
SENSE
/ V
LOW
Timing Diagram
Device Codes 101 & 110 Only, Overvoltage Option
t
PTO
t
PWTO
t
PTO
t
PWTO
t
PWTO
<t
PWTO
V
CC
WDI
or
ACK
RESET#
V
PRST
Watchdog Timer Timing Diagram
V
PRST
V
CC
1V
RESET1#
t
PTO
t
GLITCH
t
RPD
t
PTO
RESET2#
MR#
t
PTO
Manual Reset Operation Device Code 100 Only
V
SENSE
/ V
LOW
Timing Diagram
Device Codes 101 & 110 Only, Undervoltage Option
V
CC
/ RESET# Timing Diagram
t
MR
2046 Fig08 2.0
16
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
AC OPERATING CHARACTERISTICS
Under recommended Operating Conditions
l
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6
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8
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3
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4
.
6
s
t
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M
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p
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l
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0
5
s
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t
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E
S
E
R
5
s
Note 1: Minimum and maximum values for these parameters may change without notice.
2046 ACElect Table 2.0
17
2048 2.4. 3/1/01
SMS24
SUMMIT MICROELECTRONICS, Inc.
ORDERING INFORMATION
PACKAGE
8 PIN SOIC PACKAGE
SMS24
S
1
R1R1 R0R0
Base Part Number
Device Code
Register 0 Contents
Register 1 Contents
Package
1 6
(HEX Format)
(HEX Format)
2046 Tree 1.0
.05 (1.27) TYP.
1
8 Pin SOIC
0.150 - 0.157
(3.80 - 4.00)
0.189 - 0.196
(4.80 - 5.00)
0.053 - 0.069
(1.35 - 1.75)
0.013 - 0.020
(0.33 - 0.51)
0.004 - 0.010
(0.10 - 0.25)
0.016 - 0.050
(0.40 - 1.27)
45
0.010 - 0.020
(0.25 - 0.50)
0.228 - 0.244
(5.80 - 6.20)
Ref. JEDEC MS-012
Inches
(Millimeters)
18
SMS24
2048 2.4. 3/1/01
SUMMIT MICROELECTRONICS, Inc.
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating
parameters, and may vary depending upon a user's specific application. While the information in this publication has
been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any
error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications
where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to
significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless
SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is
adequately protected under the circumstances.
Copyright 2001 SUMMIT Microelectronics, Inc.
Supersedes all previous versions.
I2C is a trademark of Philips Corporation.
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