1
HV214
HV214
250V Low Charge Injection
8-Channel High Voltage Analog Switch
Features
HVCMOS
technology for high performance
Very low quiescent power dissipation 10
A
Low parasitic capacitances
DC to 10MHz analog signal frequency
-60dB typical output off isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
Flexible high voltage supplies
Surface mount package available
General Description
The Supertex HV214 is a low charge injection 8-channel high
voltage analog switch integrated circuit (IC) intended for use in
applications requiring high voltage switching controlled by low
voltage control signals, such as medical ultrasound imaging,
piezoelectric transducer drivers, inkjet printer heads and optical
MEMS modules.
Input data is shifted into an 8-bit shift register that can then be
retained in an 8-bit latch. To reduce any possible clock feedthrough
noise, the latch enable bar should be left high until all bits are
clocked in. Data are clocked in during the rising edge of the clock.
Using HVCMOS
technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
The device is suitable for various combinations of high voltage
supplies, e.g., V
PP
/V
NN
: +40V/-210V, +125V/-125V, +210V/-40V.
07/26/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Initial Release
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
Block
Diagram
D
LE
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
V
NN
V
PP
CL
V
DD
D
OUT
CLK
D
IN
8 BIT
SHIFT
REGISTER
LATCHES
LEVEL
SHIFTERS
OUTPUT
SWITCHES
CL
CL
CL
CL
CL
CL
CL
CL
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
LE
3
HV214
Electrical Characteristics
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2
Absolute Maximum Ratings*
V
DD
Logic power supply voltage
-0.5V to +15V
V
PP
- V
NN
Supply voltage
260V
V
PP
Positive high voltage supply
-0.5V to V
NN
+250V
V
NN
Negative high voltage supply
+0.5V to -260V
Logic input voltages
-0.5V to V
DD
+0.3V
Analog Signal Range
V
NN
to V
PP
Peak analog signal current/channel
2.5A
Storage temperature
-65
C to +150
C
Power dissipation
28-pin PLCC
1.2W
48 lead TQFP
1.0W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
4
HV214
Symbol
Parameter
Value
V
DD
Logic power supply voltage
4.5V to 13.2V
V
PP
Positive high voltage supply
40V to V
NN
+ 250V
V
NN
Negative high voltage supply
-40V to -210V
V
IH
High-level input voltage
V
DD
-1.5V to V
DD
V
IL
Low-level input voltage
0V to 1.5V
V
SIG
Analog signal voltage peak to peak
V
NN
+10V to V
PP
-10V
T
A
Operating free air-temperature
0
C to 70
C
Power Up/Down Sequence:
1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2 V
SIG
must be V
NN
V
SIG
V
PP
or floating during power up/down transistion.
3 Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0msec.
Operating Conditions
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L
H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift
register data flows through the latch.
4. D
OUT
is high when switch 7 is on.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
D0
D1
D2
D3
D4
D5
D6
D7
LE
CL
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
L
L
L
OFF
H
L
L
ON
X
X
X
X
X
X
X
X
H
L
HOLD PREVIOUS STATE
X
X
X
X
X
X
X
X
X
H
OFF OFF OFF OFF OFF OFF OFF OFF
Truth Table
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