1
HV450
Absolute Maximum Ratings*
V
NN1
, power supply voltage
-240V
V
PP
, P-channel gate voltage supply
-20V
V
NN2
, N-channel gate voltage supply
V
NN1
+20V
V
DD
, logic supply
+7.5V
Storage temperature
-65C to +150C
Power dissipation
600mW
* All voltages referenced to ground
Operating Voltage
Package Options
V
NN1
SOW-16
-220V
HV450WG
General Description
The Supertex HV450 is a PWM high voltage ring generator. The
high voltage output P- and N-channel transistors are controlled
independently by the logic inputs P
IN
and N
IN
. For application
where a single control pin (N
IN
) is desired, the mode pin should
be connected to Gnd. This adds a 200ns deadband on the
control logic to avoid cross conduction on the high voltage
output. A logic high on N
IN
will turn the high voltage P-Channel on
and the N-Channel off. The outputs can drive up to 5 RENs. The
HV450 can drive external MOSFETs for applications requiring
larger loads. The IC can be powered down by connecting the
enable pin to V
DD
. The high voltage outputs have pulse by pulse
over current protection.
Ordering Information
High-Voltage Ring Generator
Features
Integrated high voltage transistors
67V
RMS
ring signal
Output over current protection
Can drive external MOSFETs for larger loads
Applications
High voltage ring generator
Set-top/Street box ring generator
Pair gain ring generator
Pin Configuration
top view
SOW-16
N/C
P
GND
GND
Mode
P
IN
N
IN
EN
V
DD
V
PP
P
GATE
V
PSEN
HV
OUT
V
NSEN
N
GATE
V
NN2
V
NN1
1
8
2
3
4
5
6
7
16
9
15
14
13
12
11
10
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
2
Symbol Parameters
Min
Typ
Max
Unit
Conditions
V
PP
P-channel linear regulator output voltage
-10
-18
V
V
NN1
High voltage negative supply
- 220
-110
V
V
NN2
Negative linear regulator output voltage V
NN1
+ 6.0
V
NN1
+ 10.0
V
V
DD
Logic supply voltage
4.5
5.5
V
I
NN1Q
V
NN1
quiescent current
300
500
A
P
IN
= N
IN
= EN = L
25
P
IN
= N
IN
= L, EN = H
I
DDQ
V
DD1
quiescent current
90
200
A
P
IN
= N
IN
= EN = L
35
100
P
IN
= N
IN
= L, EN = H
I
NN1
V
NN1
operating current
1.4
mA
No load, V
OUTP
and V
OUTN
switching at
100KHz
I
DD
V
DD
operating current
1.0
mA
I
IL
Mode logic input low current
25
A
Mode = 0V
V
IL
Logic input low voltage
0
1.0
V
V
DD
= 5.0V
V
IH
Logic input high voltage
4.0
5.0
V
V
DD
= 5.0V
High Voltage Output
Symbol Parameters
Min
Typ
Max
Unit
Conditions
R
SOURCE
V
OUT
P source resistance
65
I
OUT
= 100mA
R
SINK
V
OUT
P sink resistance
65
I
OUT
= -100mA
t
d(ON)
HV
OUT
delay time
150
ns
P
IN
= high to low, Mode = high
t
rise
HV
OUT
rise time
50
ns
P
IN
= high to low
t
d(OFF)
HV
OUT
delay time
200
ns
N
IN
= low to high, Mode = high
t
fall
HV
OUT
fall time
50
ns
N
IN
= low to high
t
db
Logic deadband time
250
ns
Mode = low
V
psen
HV
OUT
current source sense voltage
-1.2
-0.8
V
V
nsen
HV
OUT
current sink sense voltage
V
NN1
+ 0.8
V
NN1
+ 1.2
V
t
shortP
HV
OUT
off delay time when current
70
150
ns
source sense is activiated
t
shortN
HV
OUT
off delay time when current sink
70
150
ns
sense is activated
t
whout
Minimum pulse width for HV
OUT
at P
GND
500
ns
t
wlout
Minimum pulse width for HV
OUT
at V
NN1
500
ns
Electrical Characteristics
(Over operating supply voltages unless otherwise specified, T
A
= -40C to +85C.)
Truth Table
N
IN
P
IN
Mode
EN
HV
OUT
L
L
H
L
Pgnd
L
H
H
L
High Z
H*
L*
H
L
*
H
H
H
L
V
NN1
L
X
L
L
V
NN1
H
X
L
L
Pgnd
X
X
X
H
High Z
*This state will short V
NN1
to Pgnd and should therefore be avoided.
HV450
3
Block Diagram
High
Voltage
Level
Translator
Logic
Linear
Reg
P
GND
V
DD
V
DD
P
IN
N
IN
EN
Mode
GND
V
psen
P
gate
V
PP
HV
OUT
Current
Sense
and
Driver
Current
Sense
and
Driver
Linear
Reg
V
NN2
V
nsen
N
gate
V
NN1
High
Voltage
Level
Translator
Pin Description
V
PP
P-channel gate voltage supply. Generated by an internal linear regulator. A 0.1F capacitor should be connected between
P
GND
and V
PP
.
V
NN1
Negative high voltage supply.
V
NN2
N-channel gate voltage supply. Generated by an internal linear regulator. A 0.1F capacitor should be connected between
V
NN2
and V
NN1
.
V
DD
Logic supply voltage.
GND
Low voltage ground.
P
GND
High voltage power ground.
P
IN
Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel.
N
IN
Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel.
EN
Logic enable input. Logic low enables IC.
Mode
Logic mode input. Logic low activates 200nsec deadband. When mode is low, N
IN
turns on and off the high voltage N- and
P-Channels. Pin is not used and should be connected to V
DD
or ground.
HV
OUT
High voltage output. Voltage swings from P
GND
to V
NN1
.
V
psen
Pulse by pulse over current sensing for P-Channel MOSFET.
V
nsen
Pulse by pulse over current sensing for N-Channel MOSFET.
P
gate
Gate drive for external P-channel MOSFET.
N
gate
Gate drive for external N-channel MOSFET.
HV450
4
Typical Application Circuit
High
Voltage
Level
Translator
Linear
Reg
P
gnd
V
DD
V
DD
GND
V
psen
P
gate
V
PP
HV
OUT
10mH
3.9
3.9
0.1
F
0.22
F
Sine Wave
Ring Output
Current
Sense
and
Driver
Current
Sense
and
Driver
Linear
Reg
Logic
N
IN
P
IN
Mode
EN
V
NN2
V
nsen
N
gate
V
NN1
0.1
F
High
Voltage
Level
Translator
-Controller
Feedback
Network
HV450
HV450
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
12/13/010
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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