1
03/13/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Features
Processed with HVCMOS Technology
Output voltages to -300V
Source current minimum 60 mA
Shift register speed 8 MHz
Polarity and blanking inputs
CMOS compatible inputs
Forward and reverse shifting options
44-lead plastic and ceramic surface mount packages
Hi-Rel processing available
Can be used with the HV55 and HV56 to provide 300V
push pull operation
General Description
The HV45 and HV46 are low-voltage serial to high-voltage
parallel converters with P-Channel open drain outputs. These
devices have been designed for use as drivers for AC-electrolu-
minescent displays. They can also be used in any application
requiring multiple output high-voltage current source capabilities
such as driving inkjet and electrostatic print heads, plasma
panels, or vacuum fluorescent displays.
These devices consist of a 32-bit shift register, 32 data latches,
and control logic to perform polarity and blanking functions. Data
is shifted through the shift register on the logic high-to-low
transition of the clock. The HV45 shifts in the counterclockwise
direction when viewed from the top of the package and the HV46
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. The data in the shift register is
latched when the latch enable pin is brought to logic high and then
returned to ground. If the latch enable pin is held high, the latch
becomes transparent and the shift register data is directly re-
flected in the outputs.
For applications requiring active pull down as well as pull up, the
HV45 and HV46 can be paired with the HV55 and HV56 devices,
respectively.
Absolute Maximum Ratings
1
Supply voltage, V
DD
+0.5V to -16V
Off state output voltage
HV4630
+0.5V to -315V
HV4622
+0.5V to -240V
Logic input levels
+0.5V to V
DD
- 0.3V
Ground current
2
1.5A
Continuous total power dissipation
3
1200mW
Operating temperature range
-40
C to +85
C
Storage temperature range
-65
C to +150
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. All voltages are referenced to V
SS
.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25
C ambient derate linearly to maximum operating
temperature at 20mW/
C for plastic and at 15mW/
C for ceramic.
HV4530
HV4630
32-Channel Serial To Parallel Converter
with P-Channel Open Drain Outputs
Package Options
44 J-Lead Quad
44 Quad Plastic
Die
Plastic Chip Carrier
Gullwing
HV4530
-300
HV4530PJ
HV4530PG
HV4530X
HV4630
-300
HV4630PJ
HV4630PG
HV4630X
Ordering Information
Recommended
Device
Operating
V
PP
Max
2
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
8
MHz
t
WH
/t
WL
Clock width high or low
62
ns
t
SU
Data set-up time before clock rises
50
ns
t
H
Data hold time after clock rises
20
ns
t
ON
Turn ON time, HV
OUT
from enable
400
ns
R
L
= 10K to V
OO
MAX
t
DHL
Delay time clock to data high to low
100
ns
C
L
= 15pF
t
DLH
Delay time clock to data low to high
100
ns
C
L
= 15pF
t
DLE
Delay time clock to LE low to high
50
ns
t
WLE
Width of LE pulse
50
ns
t
SLE
LE set-up time before clock falls
50
ns
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
-15
mA
f
CLK
= 8 MHz
F
DATA
= 4 MHz
I
DDQ
Quiescent V
DD
supply current
-100
A
V
IN
= V
SS
or V
DD
I
O(OFF)
Off state output current
-100
A
All SWS parallel
I
IH
High-level logic input current
-1
A
V
IH
= V
DD
I
IL
Low-level logic input current
+1
A
V
IL
= V
SS
V
OH
High-level output data out
V
DD
+ 1.0V
V
I
Dout
= -100
A
V
OL
Low-level output voltage
HV
OUT
-30.0
V
I
HVout
= -60mA
Data out
-1.0
V
I
Dout
= -100
A
V
OC
HV
OUT
clamp voltage
+1.5
V
I
OL
= +60mA
Electrical Characteristics
1
(over recommended operating conditions unless noted)
HV4530//HV4630
DC Characteristics
AC Characteristics
(V
DD
= -12V, T
C
= 25
C)
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
-10.8
-13.2
V
HV
OUT
Output off voltage
+0.3
-300
V
V
IH
High-level input voltage (LOGIC "1")
V
DD
+ 2V
V
DD
V
V
IL
Low-level input voltage (LOGIC "0")
0
-2.0
V
f
CLK
Clock frequency
8
MHz
T
A
Operating free-air temperature
-40
+85
C
Note: All voltages are referenced to V
SS
.
4
Polarity
Blanking
Latch Enable
Data Input
Clock
Data Out
32-Bit
Shift
Register
HV
OUT
1
(Outputs 3 to 30
not shown)
Latch
Latch
HV
OUT
2
HV
OUT
31
HV
OUT
32
Latch
Latch
V
SS
Functional Block Diagram
HV4530//HV4630
Function Table
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
1
2
...
32
1
2
...
32
*
All on
X
X
X
L
L
*
*
...
*
ON
ON
...
ON
*
All off
X
X
X
L
H
*
*
...
*
OFF OFF
...
OFF
*
Invert mode
X
X
L
H
L
*
*
...
*
*
*
...
*
*
Load S/R
H or L
L
H
H
H or L *
...
*
*
*
...
*
*
X
H or L
H
H
*
*
...
*
*
*
...
*
*
X
H or L
H
L
*
*
...
*
*
*
...
*
*
L
H
H
H
L
*
...
*
OFF
*
...
*
*
H
H
H
H
H
*
...
*
ON
*
...
*
*
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant,
= high-to-low transition,
= low-to-high transition.
* = dependent on previous stage's state before the last CLK high-to-low transition or last LE high.
Data
CLK
LE
BL
POL
Load
latches
Transparent
latch mode
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