1
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV506
Preliminary
80-Lead
64-Lead 3-Sided
Ceramic Gullwing
Plastic Gullwing
Die
General Description
The HV506 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. It is especially suitable for use as
a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DR
IO
) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR
IO
can be
triggered at any time. The DIR pin controls the direction of data
through the device. When DIR is at logic high, DR
IOA
is the input
and DR
IOB
is the output. When DIR is grounded, DR
IOB
is the input
and the DR
IOA
is the output. See the Output Sequence Operation
Table for output sequence. The POL and OE pins perform the
polarity select and output enable function respectively. Data is
clocked through the shift register loaded on the low to high
transition of the clock. A logic high in the shift register will cause
the other corresponding output to swing to V
DD
if POL is high, or
to V
SS
if POL is low. All other outputs will be in the High-Z state.
If OE is at logic high all outputs will be in the High-Z state. An
output in the High-Z state may block up to 275V above V
SS
or
275V below V
DD
. The D
P
/D
N
pins are for the positive/negative
discharge of the high voltage output HV
OUT
. Data output buffers
are provided for cascading devices.
LV
DD
requires low current for the HV506 logic section. V
DD
requires high current for the output section . Typically these two
pins are at the same potential. The same current and potential
conditions apply to the LV
SS
, logic, and V
SS
, output pins. V
sub
must
always be equal or greater than the most positive supply.
Features
Processed with HVDI
technology
Symmetric row drive
Output voltage up to 275V
Source/Sink current 300mA (min.)
Shift Register Speed 3MHz
Pin-programmable shift direction (DIR)
Hi-Rel processing available
Absolute Maximum Ratings
Logic supply voltage, LV
DD
1
-0.5V to +15V
Output supply voltage, V
DD
1
-0.5V to +15V
Substrate bias voltage, V
sub
See Note 3
Output voltage, HV
OUT
300V
Logic input levels
-0.5V to V
DD
+0.5V
Continuous total power dissipation
2
Ceramic
1900mW
Plastic
1200mW
Operating temperature range
Plastic
-40C to +85C
Ceramic -55C to +125C
Storage temperature range
-65C to +150C
Lead temperature 1.6mm (1/16 inch)
260C
from case for 10 seconds
Notes:
1. All voltages are referenced to V
SS
.
2. For operation above 25C ambient derate linearly to maximum operating
temperture at 20mW/C for plasitc and at 19mW/C for ceramic.
3. V
sub
must be the most positive with respect to V
SS
.
Ordering Information
Package Options
Device
HV506
HV506DG
HV506PG
HV506X
275V 40-Channel Row Driver with SCR Outputs
2
Electrical Characteristics
(over recommended operating conditions of V
DD
= 12V, LV
DD
= 12V, and T
A
= 25C unless noted)
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
10
mA
f
CLK
= 3MHz
I
DDQ
Quiescent V
DD
supply current
100
A
All V
IN
= V
SS
or V
DD
V
OH
High-level output
HV
OUT
V
DD
-10
V
I
O
= -300mA
Data out
10.8
V
I
O
= -100A
V
OL
Low-level output
HV
OUT
V
SS
+10
V
I
O
= 300mA
Data out
1.2
V
I
O
= 100A
I
IH
High-level logic input current
1
A
V
IH
= V
DD
I
IL
Low-level logic input current
-1
A
V
IL
= V
SS
I
OFF
Output OFF leakage current (High-Z)
10
A
HV
OUT
- V
SS
= 275V,
V
sub
= HV
OUT
10
A
V
DD
- HV
OUT
= 275V,
V
sub
= V
DD
Notes:
1. Only one output can be turned on at a time.
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
V
OH
High-level output
V
DD
-10
V
I
O
= -300mA
V
OL
Low-level output
V
SS
+10
V
I
O
= 300mA
I
L
Latching Current
15
mA
V
L
Latching Voltage
100
V
I
H
Holding Current
10
mA
V
H
Holding Voltage
10
V
I
OFF
Output OFF leakage current (High-Z)
10
A
HV
OUT
- V
SS
= 275V,
V
sub
= HV
OUT
10
A
V
DD
- HV
OUT
= 275V,
V
sub
= V
DD
SCR Characteristics
3
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
3
MHz
t
W (H/L)
Pulse width - clock high or low
150
ns
t
SUD
Data set-up time before clock rises
50
ns
t
HD
Data hold time after clock rises
50
ns
t
SUC
HV
OUT
delay from clock rises (Hi-Z to H or L)
1
s
C
L
= 10nF
t
SUE
HV
OUT
delay from Output Enable rises
600
ns
C
L
= 10nF
t
HC
HV
OUT
delay from clock rises (H or L to Hi-Z)
2
s
C
L
= 10nF
t
HE
HV
OUT
delay from Output Enable rises
600
ns
C
L
= 10nF
t
DHL
*
Delay time clock to data output falls
250
ns
C
L
= 15pF
t
DLH
*
Delay time clock to data output rises
250
ns
C
L
= 15pF
t
OFF(SCR)
Turn off time of output SCR
4
s
Time after I
OUT
2mA,
C
L
= 10nF
t
OFF(D)
Turn off time of output diode
2
s
Time after I
OUT
2mA,
C
L
= 10nF
t
POW
POL pulse width
3
s
t
OEW
Output Enable pulse width
3
s
SR
Slew rate of HV
OUT
200
V/s
AC Characteristics
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
. Therefore the delay is measured from the trailing edge of the clock.
HV506
4
Symbol
Parameter
Min
Max
Units
LV
DD
Logic supply voltage
10.8
13.2
V
V
DD
Output supply voltage
10.8
13.2
V
V
IH
High-level input voltage
0.8LV
DD
LV
DD
V
V
IL
Low-level input voltage
0
0.2LV
DD
V
f
CLK
Clock frequency
3
MHz
I
O
High voltage output current
300
mA
T
A
Operating free-air temperature
Plastic
-40
+85
C
Ceramic
-55
+125
C
I
OD
Allowable pulse current through diodes
500
mA
Notes:
The substrate pin V
sub
(pin 39) must be biased for proper output breakdown voltage. V
sub
V
DD
or HV
OUT
whichever is higher.
LV
DD
/V
DD
are measured with respect to LV
SS
/V
SS
.
Recommended Operating Conditions
LV
DD
LV
SS
Input
V
DD
HV
OUT
D
N
D
P
V
SS
Logic Inputs
Data Out
Logic Data Output
High Voltage Outputs
LV
DD
LV
SS
Input and Output Equivalent Circuits
SCR Characteristics
V
L
V
H
I
L
I
H
I
V
HV506
5
HV506
Switching Waveforms
Data Reset Input
(DR
IOA
/DR
IOB
)
50%
50%
t
POW
Data Reset Output
(DR
IOA
/DR
IOB
)
t
HD
50%
50%
V
IH
V
IL
90%
10%
HV
OUT
HV
OUT
t
SUE
90%
t
HE
10%
50%
t
DLH
50%
t
DHL
50%
t
OEW
50%
High Impedance
High Impedance
High Impedance
High Impedance
90%
10%
t
SUC
90%
t
HC
10%
HV
OUT
(POL = H)
HV
OUT
(POL = L)
POL
OE
Data
Valid
t
SUD
CLK
t
WL
1/f
CLK
50%
50%
50%
50%
t
WH
t
SUC
t
HC
t
SUE
t
HE
V
IH
V
IL
V
OH
V
OH
V
OL
V
IH
V
IL
V
OL
V
IH
V
IL
V
OH
V
OL
6
HV506
DIR
Data Reset In Data Reset Out
HV
OUT
# Sequence
Direction
3
L
DR
IOB
DR
IOA
1
40 1
H
DR
IOA
DR
IOB
2
1 40
CLK
S/R
DIR
DRIOB
Output
Output
Output
VDD
LVSS
VSS
DP
HVOUT1
HVOUT2
HVOUT40
DN
LVDD
DRIOA
OE
POL
Functional Block Diagram
Function Table
I/O Relations
Inputs
CLK
DIR
S/R Data
POL
OE
HV Outputs
O/P HIGH
X
X
H
H
L
H
O/P OFF
X
X
L
X
L
HIGH-Z
O/P LOW
X
X
H
L
L
L
O/P OFF
X
X
X
X
H
All O/P HIGH-Z
Note:
H = logic high level, L = logic low level, X = irrelevant
Output Sequence Operation Table
Notes:
1. DR
IOA
is DR
IOB
delayed by 40 clock pulses.
2. DR
IOB
is DR
IOA
delayed by 40 clock pulses.
3. Reference to chip layout drawing.
7
HV506
Typical Output Circuit Connections
Substrate Bias Operation
In order to achieve the desired output breakdown voltage, the
substrate must be biased to the most positive potential of any
circuit node. For this condition, V
sub
V
DD
or HV
OUT
whichever is
higher. Refer to Typical Output Circuit Connections for wiring. A
typical V
sub
signal is shown below.
+ HV
V
sub
V
columns
-HV
0V
V
SS
HV
OUT
V
DD
V
SS
D
2
D
1
D
4
Sink SCR
Source SCR
HV506
-HV
+HV
12V
GND
D
3
D
N
D
P
+
LV
DD
LV
SS
Note: The voltage potential between LV
DD
/V
DD
and LV
SS
/V
SS
must not exceed
recommended operating conditions of 10.8V - 13.2V (12V typical)
Note: In general, when driving the outputs positive, V
SUB
= +HV. And when driving
outputs negative, V
SUB
equals most positive voltage; e.g. GND or >0V.
8
HV506
+ HV - (V
DD
- V
SS
)
V
SS
- HV
High Impedance
High Impedance
High Impedance
Output n
Output n+1
Sink*
SCR
Source*
SCR
D
2
*
t
OFF
(D
2
)
D
1
*
0V
Drive Current
Disabled
Drive Current
Disabled
t
OFF
(D
1
)
t
OFF
(Sink SCR)
t
OFF
(Source SCR)
HV Switching Waveforms and Operation
To drive a TFEL row with a negative pulse: The desired sink SCR
is enabled and V
SS
is connected to -HV via a current limited
switch. After holding the output at the -HV level, the switch is
opened in order to set the sink SCR current to zero. The row is
then discharged through a discharge diode when D
2
is switched
to GND. The application of a positive pulse to a row operates in
a similar manner using the selected source SCR and D
1
.
*
Notes internal device handling current flow. Refer to Typical Output Circuit Connections for schematic.
9
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
12/13/010
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV506
Option A:
Pin
Function
Pin
Function
1
HV
OUT
1
33
OE
2
HV
OUT
2
34
POL
3
HV
OUT
3
35
LV
DD
4
HV
OUT
4
36
V
SS
5
HV
OUT
5
37
V
DD
6
HV
OUT
6
38
LV
SS
7
HV
OUT
7
39
V
sub
8
HV
OUT
8
40
N/C
9
HV
OUT
9
41
N/C
10
HV
OUT
10
42
D
N
11
HV
OUT
11
43
D
P
12
HV
OUT
12
44
N/C
13
HV
OUT
13
45
HV
OUT
21
14
HV
OUT
14
46
HV
OUT
22
15
HV
OUT
15
47
HV
OUT
23
16
HV
OUT
16
48
HV
OUT
24
17
HV
OUT
17
49
HV
OUT
25
18
HV
OUT
18
50
HV
OUT
26
19
HV
OUT
19
51
HV
OUT
27
20
HV
OUT
20
52
HV
OUT
28
21
N/C
53
HV
OUT
29
22
D
P
54
HV
OUT
30
23
D
N
55
HV
OUT
31
24
N/C
56
HV
OUT
32
25
N/C
57
HV
OUT
33
26
LV
SS
58
HV
OUT
34
27
V
DD
59
HV
OUT
35
28
DIR
60
HV
OUT
36
29
V
SS
61
HV
OUT
37
30
CLOCK
62
HV
OUT
38
31
DR
IOA
63
HV
OUT
39
32
DR
IOB
64
HV
OUT
40
Note: Pins 6580 are NC.
Pin Configurations
Package Outline
Index
1
24
64
41
25
40
top view
3-sided Plastic 64-pin Gullwing Package
HV506
PDF 
ZIP