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12/13/01
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HV510
Package Options
Recommended Operating
Device
V
PP
Max
24 Lead SOW
Die
HV510
240V
HV510WG
HV510X
General Description
The HV510 is a low voltage serial to high voltage parallel con-
verter with 12 high voltage push-pull outputs. This device has
been designed to drive small capacitive loads such as piezo
electric transducers. It can also be used in any application
requiring multiple high voltage outputs, low current sourcing and
sinking capabilities.
The device consists of a 12-bit shift register, 12 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D
IOA
is Data In and D
IOB
is Data Out;
data is shifted from HV
OUT
12 to HV
OUT
1. When DIR is at logic high,
D
IOB
is Data In and D
IOA
is Data Out: data is then shifted from
HV
OUT
1 to HV
OUT
12. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE, BL, or the POL inputs. Transfer of data from
the shift register to the latch occurs when the LE is high. The data
in the latch is stored during LE transition from high to low.
Ordering Information
240V, 12-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Features
HVCMOS
technology
Operating output voltage of 240V
Low power level shifting from 5V to 240V
Shift register speed 8MHz @ V
DD
= 5V
12 latched data outputs
Output polarity and blanking
CMOS compatible inputs
Forward and reverse shifting options
Absolute Maximum Ratings
1
Supply voltage, V
DD
-0.5V to +6V
Supply voltage, V
PP
V
DD
to 260V
Logic input levels
-0.5V to V
DD
+0.5V
Ground current
3
0.3A
High voltage supply current
2
0.25A
Continuous total power dissipation
3
750mW
Operating temperature range
-40
C to +85
C
Storage temperature range
-65
C to +150
C
Notes
:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25
C ambient derate linearly to 85
C at 12mW/
C.
2
HV510
Symbol
Parameter
Min
Typ
Max
Units
Conditions
f
CLK
Clock frequency
8
MHz
t
W
Clock width high and low
62
ns
t
SU
Data setup time before clock rises
35
ns
t
H
Data hold time after clock rises
30
ns
t
WLE
Width of latch enable pulse
80
ns
t
DLE
LE delay time after rising edge of clock
35
ns
t
SLE
LE setup time before rising edge of clock
40
ns
t
ON
, t
OFF
Time from latch enable to HV
OUT
6.0
s
C
L
= 20pF
t
DHL
Delay time clock to data out high to low
125
ns
C
L
= 20pF
t
DLH
Delay time clock to data out low to high
125
ns
C
L
= 20pF
t
r
, t
f
All logic inputs
5
ns
Note:
1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
I
DD
V
DD
supply current
4
mA
f
CLK
= 8MHz, f
DATA
= 4MHz
LE = LOW
I
DDQ
Quiescent V
DD
supply current
200
A
All V
IN
= 0V or V
DD
I
PP
High voltage supply current
0.25
mA
V
PP
= 240V All outputs high
0.25
mA
V
PP
= 240V All outputs low
I
IH
High-level logic input current
10
A
V
IH
= V
DD
I
IL
Low-level logic input current
-10
A
V
IL
= 0V
V
OH
High-level output
HV
OUT
220
V
V
PP
= 240V, IHV
OUT
= -0.5mA
175
V
V
PP
= 200V, lHV
OUT
= -0.5mA
Data out
V
DD
-1V
V
I
DOUT
= -100
A
V
OL
Low-level output
HV
OUT
25
V
V
DD
= 5V, IHV
OUT
= 1mA
Data out
1.0
V
I
DOUT
= 100
A
V
OC
HV
OUT
clamp voltage
V
PP
+1.5
V
I
OL
= 1mA
-1.5
V
I
OL
= -1mA
I
OH
Output Source Current
1.0
mA
V
PP
= 240V
0.8
mA
V
PP
= 200V
Symbol
Parameter
Min
Typ
Max
Units
V
DD
Logic supply voltage
4.5
5.0
5.5
V
V
PP
High voltage supply
60
240
V
V
IH
High-level input voltage
V
DD
-0.9
V
DD
V
V
IL
Low-level input voltage
0
0.9
V
T
A
Operating free-air temperature
-40
+85
C
Notes:
Power-up sequence should be the following:
1. Connect ground.
4.
Apply V
PP
.
2. Apply V
DD
.
5.
The V
PP
should not drop below V
DD
or float during operation.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(for V
DD
= 5V, V
PP
= 240V, T
A
= 25
0
C)
DC Characteristics
Recommended Operating Conditions
AC Characteristics
1
(For V
DD
= 5V, V
PP
= 200V, T
A
= 25
C)
4
HV510
HV
OUT
2
8 Additional
Outputs
POL
BL
LE
CLK
12-bit
Static Shift
Register
12 Latches
HV
OUT
11
V
PP
HV
OUT
1
DIR
D
IOA
D
IOB
HV
OUT
12
L/T
L/T
L/T
L/T
Functional Block Diagram
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
1
2
...
12
1
2
...
12
*
All on
X
X
X
L
L
X
*
*
...
*
H
H
...
H
*
All off
X
X
X
L
H
X
*
*
...
*
L
L
...
L
*
Invert mode
X
X
L
H
L
X
*
*
...
*
*
*
...
*
*
Load S/R
H or L
L
H
H
X
H or L *
...
*
*
*
...
*
*
Store data
X
X
H
H
X
*
*
...
*
*
*
...
*
*
in latches
X
X
H
L
X
*
*
...
*
*
*
...
*
*
Transparent
L
H
H
H
X
L
*
...
*
L
*
...
*
*
latch mode
H
H
H
H
X
H
*
...
*
H
*
...
*
*
D
IOA
X
X
X
L
Q
n
Q
n-1
--
D
IOB
D
IOB
X
X
X
H
Q
n
Q
n+1
--
D
IOA
Notes:
H = high level, L = low level, X = irrelevant,
= low-to-high transition,
= high-to-low transition.
* = dependent on previous stage's state before the last CLK or last LE high.
Data
CLK
LE
BL
POL
DIR
I/O relation
Function Table
L/T = Level Translator
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