1
General Description
The HV574 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. This device has been designed for
use as a driver for printer applications. It can also be used in any
application requiring multiple output high-voltage current sour-
cing and sinking capability such as driving plasma panels, vac-
uum fluorescent displays, or large matrix LCD displays.
The device has 4 parallel 20-bit dynamic shift registers, permitting
data rates 4X the speed of one ( they are clocked together).
There are 80 static latches and control logic to perform the polarity
select and blanking of the outputs. HV
OUT
1 is connected to the first
stage of the first shift register through the polarity and blanking
logic. Data is shifted through the shift registers on the logic low to
high transition of the clock. The DIR pin causes CCW shifting
when connected to GND, and CW shifting when connected to
V
DD
. A data output buffer is provided for cascading devices. This
output reflects the current status of the last bit of the shift register
(HV
OUT
80). Operation of the shift register is not affected by the LE
(latch enable), BL (blanking), or the POL (polarity) inputs. Trans-
fer of data from the shift registers to the latches occurs when the
LE (latch enable) input is high. The data in the latches is stored
when LE is low.
Absolute Maximum Ratings
Supply voltage, V
DD
1
-0.5V to +7.5V
Output voltage, V
PP
1
-0.5V to +90V
Logic input levels
1
-0.3V to V
DD
+0.3V
Ground current
2
1.5A
Continuous total power dissipation
3
1200mW
Operating temperature range
-40 to 85
C
Storage temperature range
-65
C to +150
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Limited by the total power dissipated in the package.
3. For operation above 25
C ambient derate linearly to 85
C at 20mW/
C.
HV574
Device
100 Lead Quad
Plastic Gullwing
Die
HV574
HV574PG
HV574X
100 MHz, 80-Channel Serial To Parallel Converter
With Push-Pull Outputs
Ordering Information
Package Options
Features
Processed with HVCMOS
technology
5V CMOS logic
Output voltages up to 80V
Low power level shifting
100MHz equivalent data rate using four dynamic
shift registers
Static latched data outputs
Forward and reverse shifting options (DIR pin)
Diode to V
PP
allows efficient power recovery
Outputs may be hot switched
Hi-Rel processing available
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV574
Electrical Characteristics
(over recommended commercial operating conditions unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
30
mA
V
DD
= V
DD
max
f
CLK
= 25MHz
I
PP
Quiescent V
PP
supply current
100
A
Outputs high
100
A
Outputs low
I
DDQ
Quiescent V
DD
supply current
100
A
All V
IN
= V
DD
V
OH
High-level output
HV
OUT
V
PP
- 9V
V
I
O
= -30mA, V
PP
= 80V
Data out
V
DD
- 0.5
V
I
O
= -100
A
V
OL
Low-level output
HV
OUT
3.75
V
I
O
= 15mA, V
DD
= 5V
Data out
0.5
V
I
O
= 100
A
I
IH
High-level logic input current
1.0
A
V
IH
= V
DD
I
IL
Low-level logic input current
-1.0
A
V
IL
= 0V
AC Characteristics
(T
A
= 85
C max. Logic signal inputs and Data inputs have t
r
, t
f
5ns [10% and 90% points])
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
0.001
25
MHz
V
DD
= 4.5V, T
J
= 25
C
0.001
20
V
DD
= 4.5V, T
J
= 125
C
t
WL
,t
WH
Clock width high or low
20
ns
t
SU
Data set-up time before clock rises
0
ns
t
H
Data hold time after clock rises
15
ns
t
ON
, t
OFF
Time from latch enable to HV
OUT
500
ns
C
L
= 15pF
t
DHL
Delay time clock to data high to low
38
ns
C
L
= 15pF, V
DD
= 5.0V
t
DLH
Delay time clock to data low to high
38
ns
C
L
= 15pF, V
DD
= 5.0V
t
DLE
*
Delay time clock to LE low to high
25
ns
t
WLE
Width of LE pulse
25
ns
t
SLE
LE set-up time before clock rises
0
ns
tr, tf
Output rise/fall time
1.0
s
C
L
= 600pF,
HV
OUT
from 0 to 60V
*
t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
4.5
5.5
V
V
PP
Output voltage
12
80
V
V
IH
High-level input voltage
V
DD
-0.5V
V
V
IL
Low-level input voltage
0
0.5
V
f
CLK
Clock frequency per register
0.001
25
MHz
T
A
Operating free-air temperature
-40
+85
C
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operation.
Recommended Operating Conditions
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1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
11/12/01
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV574
Package Outlines
81
100
80
51
50
31
1
30
top view
100-Lead Plastic Quad Flat Package
("Gullwing" Package)
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
All O/P High
X
X
X
L
L
X
H
All O/P Low
X
X
X
L
H
X
L
O/P Normal
X
X
X
H
H
X
No inversion
O/P Inverted
X
X
X
H
L
X
Inversion
L
H
H
H
X
L
L
H
H
H
H
X
H
H
L
H
H
L
X
L
H
H
H
H
L
X
H
L
Data Stored/
X
X
L
H
H
X
*
Stored Data
Latches Loaded
X
X
L
H
L
X
*
Inversion of
Stored Data
D
IN
X
H
H
H
H
Q
n
Q
n +1
New H or L
D
OUT
X
D
IN
X
L
H
H
H
Q
n
Q
n +1
Previous
D
OUT
X
H or L
D
OUT
X
L
H
H
L
Q
n
Q
n -1
Previous
D
IN
X
H or L
D
OUT
X
H
H
H
L
Q
n
Q
n -1
New H or L
D
IN
X
Data
CLK
LE
BL
POL
DIR
Notes:
*
= dependent on previous stage's state. See Pin configuration for D
IN
and D
OUT
pin designation for CW and CCW shift.
Function Table
I/O Relation
Data Falls
Through
(Latches
Transparent)
Pin Configuration
100-Pin PG Package
Pin
Function
1
HV
OUT
30
2
HV
OUT
29
3
HV
OUT
28
4
HV
OUT
27
5
HV
OUT
26
6
HV
OUT
25
7
HV
OUT
24
8
HV
OUT
23
9
HV
OUT
22
10
HV
OUT
21
11
HV
OUT
20
12
HV
OUT
19
13
HV
OUT
18
14
HV
OUT
17
15
HV
OUT
16
16
HV
OUT
15
17
HV
OUT
14
18
HV
OUT
13
19
HV
OUT
12
20
HV
OUT
11
21
HV
OUT
10
22
HV
OUT
9
23 HV
OUT
8
24 HV
OUT
7
25 HV
OUT
6
Pin
Function
26 HV
OUT
5
27 HV
OUT
4
28 HV
OUT
3
29 HV
OUT
2
30 HV
OUT
1
31 N/C
32 V
PP
33 HVGND
34 D
IN
A
35 D
IN
B
36 D
IN
C
37 D
IN
D
38 V
DD
39 POL
40 LE
41 CLK
42 DIR
43 BL
44 GND
45 D
OUT
D
46 D
OUT
C
47 D
OUT
B
48 D
OUT
A
49 HVGND
50 V
PP
Pin
Function
51 HV
OUT
80
52 HV
OUT
79
53 HV
OUT
78
54 HV
OUT
77
55 HV
OUT
76
56 HV
OUT
75
57 HV
OUT
74
58 HV
OUT
73
59 HV
OUT
72
60 HV
OUT
71
61 HV
OUT
70
62 HV
OUT
69
63 HV
OUT
68
64 HV
OUT
67
65 HV
OUT
66
66 HV
OUT
65
67 HV
OUT
64
68 HV
OUT
63
69 HV
OUT
62
70 HV
OUT
61
71 HV
OUT
60
72 HV
OUT
59
73 HV
OUT
58
74 HV
OUT
57
75 HV
OUT
56
Pin
Function
76 HV
OUT
55
77 HV
OUT
54
78 HV
OUT
53
79 HVout52
80 HV
OUT
51
81 HV
OUT
50
82 HV
OUT
49
83 HV
OUT
48
84 HV
OUT
47
85 HV
OUT
46
86 HV
OUT
45
87 HV
OUT
44
88 HV
OUT
43
89 HV
OUT
42
90 HV
OUT
41
91 HV
OUT
40
92 HV
OUT
39
93 HV
OUT
38
94 HV
OUT
37
95 HV
OUT
36
96 HV
OUT
35
97 HV
OUT
34
98 HV
OUT
33
99 HV
OUT
32
100 HV
OUT
31
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