12-111
12
HV62106
Ordering Information
Package Options*
Device
Die in wafer form
Die in waffle pack
HV62106
HV62106XW
HV62106X
*Consult factory for availability of bumped die.
64-Channel Gray-Shade Display Column Driver
Absolute Maximum Ratings
Supply voltage, V
DD
-0.5V to +7.5V
Supply voltage, V
PP
-0.5V to +70V
Logic input levels
-0.5V to V
DD
+ 0.5V
Operating temperature range
-40
C to +85
C
Storage temperature range
-65
C to +150
C
Note:
All voltages are referenced to GND.
Features
5V CMOS inputs
64 outputs per device
Up to 60V output voltage
Capable of 4 output pulse widths
PWM gray shade conversion
Two 2-bit data buses
28 MHz data throughput rate
Pin-programmable shift direction (DIR)
Integrated high-voltage CMOS technology
Optimized layout for COG use
General Description
Not recommended for new designs.
The HV62106 is a 64-channel column driver IC designed for gray
shade flat panel displays. Using Supertex's unique HVCMOS
technology, it is capable of providing gray shading by pulse width
modulation (PWM) conversion.
A high level on the chip select input enables the IC to load data
into a set of input data latches. This input data, in two groups of
two, are latched into the input data latches on both edges of the
Shift Clock. The data stored in these input data latches is
transferred to a set of output data latches on the rising edge of
Load Count. After the input data registers are full, a chip select
output signal is provided for enabling the next IC in the chain.
A master binary counter is reset with a high level on Load Count
and is incremented on the rising edge of Count Clock. The data
stored in the output data latches is compared to the contents of
the master counter. The output of the comparator drives the high
voltage output devices. The higher the binary number in the
output data latches, the longer the pulse width will be on the
corresponding output.
DIR is a shift-direction-select input which is provided to inter-
change the direction of the latched data inputs. When the DIR
input is high, CS2 becomes chip select input and data is latched
into the data latches in the sequence of HV
OUT
1 to HV
OUT
64.
When the DIR input is low, CS1 becomes chip select input and
data is latched into the data latches in the sequence of HV
OUT
64
to HV
OUT
1. D
IN
1 and D
IN
2 load in data for odd number of outputs.
D
IN
3 and D
IN
4 load in data for even number of outputs.
12-112
Symbol
Parameter
Min
Max
Units
Conditions
f
SC
Shift clock frequency
7
MHz
f
DIN
Data In frequency
7
MHz
f
CC
Count clock frequency
3
MHz
t
WA
Chip select pulse width
80
ns
t
SS
Chip select set-up time
20
ns
t
HS
Chip select hold time
40
ns
t
DS
Data to shift clock set-up time
-10
30
ns
t
DH
Data to shift clock hold time
30
ns
t
WLC
Load count pulse width
160
ns
t
DLCC
Load count to count clock delay
70
ns
t
DSL
Shift clock to load count delay
200
ns
t
CSC
Shift clock cycle time
143
ns
t
DLC
Load count to HV
OUT
delay
1.5
s
C
L
= 15pF // R
L
= 10M
t
WCC
Count clock pulse width
160
ns
t
CCC
Count clock cycle time
333
ns
t
DCC
Count clock to HV
OUT
delay
1.5
s
C
L
= 15pF // R
L
= 10M
t
WSC
Shift clock pulse width
70
ns
t
WD
Data in pulse width
60
ns
Electrical Characteristics
(Over recommended conditions of V
DD
= 5V, V
PP
= 60V, T
A
= 25
C unless otherwise noted)
Symbol
Parameter
Min
Max
Units
Conditions
I
PPQ
Quiescent V
PP
supply current
100
A
All HV
OUT
low or high
V
OH
High-level output
50
V
I
OUT
= -12mA
V
OL
Low-level output
8
V
I
OUT
= 15mA
High Voltage DC Characteristics
AC Characteristics (Logic Timing)
HV62106
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
10
mA
f
SC
= 7MHz, f
CC
= 3MHz
I
DDQ
Quiescent V
DD
supply current
1
mA
All V
IN
= GND
I
IH
High-level input current
10
A
V
IH
= V
DD
I
IL
Low-level input current
-10
A
V
IL
= GND
I
OH
High-level output current
-1
mA
I
OL
Low-level output current
1
mA
Low Voltage DC Characteristics
12-113
Sequence
Function
Data-In
CS1/
CS2/
Shift
Load
Count Clock
HV
OUT
(D1 - D4)
CS2
CS1
Clock
Count
(RCLK, GCLK)
1
Load data from
H/L
X
L
H
L
data bus
2
Load counter
X
L
X
X
H
3
Counting/conversion
X
L
X
X
L
H/L
4
Next cycle
H/L
X
L
H
L
Symbol
Parameter
Min
Max
Units
Conditions
V
PP
High voltage supply
0
60
V
V
DD
Logic supply voltage
4.5
5.5
V
V
IL
Low-level input voltage
0
1
V
V
IH
High-level input voltage
V
DD
-1
V
DD
V
f
SC
Shift clock frequency
7
MHz
f
CC
Count clock frequency
3
MHz
T
A
Operating temperature
-40
+85
C
Recommended Operating Conditions
Pad Definitions
HV62106
Function Table
Pad #
Name
I/O
Function
2 - 5
D
IN
1 - D
IN
4
I
Inputs for binary-format parallel data
18 -21
(D
IN
2
and D
IN
4
are the most significant bits)
23, 33
Shift Clock
I
Latching data on both edges
24, 32
CS1
I/O
Input when DIR = 0; Output when DIR = 1
10, 22
CS2
I/O
Output when DIR = 0; Input when DIR = 1
8, 15
Load Count
I
Initiates the conversion
26, 30
DIR
I
Controls the data shift directions
27, 29
GND
--
Logic ground
14, 28
HVGND
--
High voltage ground
1, 41
V
PP
--
High voltage supply
42-105
HV
OUT
1 64
O
High voltage outputs
25, 31
V
DD
--
Logic supply voltage
6, 17
Count Clock
I
Input for incrementing the master counter for the green pixel
(GCLK)
7, 16
Count Clock
I
Input for incrementing the master counter for the red pixel
(RCLK)
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