1
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Device
Features
Processed with HVCMOS
technology
32 push-pull CMOS output up to 32V
Low power level shifting
Source/sink current minimum 1mA
Shift register speed 5MHz
Latched data outputs
Bidirectional shift register (DIR)
Backplane output
32-Channel LCD Driver
with Separate Backplane Output
HV66
General Description
Not recommended for new designs.
The HV66 is a low-voltage serial to high-voltage parallel converter
with push-pull outputs. This device has been designed for use as
a driver circuit for LCD displays. It can also be used in any
application requiring multiple output high-voltage current sourc-
ing and sinking capabilities. The inputs are fully CMOS compat-
ible.
The device consists of a 32-bit shift register, 32 latches, and
control logic to perform blanking and polarity control of the
outputs. HVout1 is connected to the first stage of the shift register.
Data is shifted through the shift register on the logic rising
transition of the clock. A DIR pin causes data shifting counter-
clockwise when grounded and clockwise when connected to V
DD
.
A data output buffer is provided for cascading devices. This output
reflects the current status of the last bit of the shift register.
Operation of the shift register is not affected by the LE (latch
enable), BL (blank) or the POL (polarity) inputs. Transfer of data
from the shift register to the latch occurs when the LE (latch
enable) input is high. The data in the latch is stored after LE
transitions from high to low.
The blank signal, BL, when pulled low, will set all outputs to the
same state as the BP
OUT
. If this signal is left open then the BL
defaults to a high state.
Ordering Information
Package Options
44 Lead Quad
44 J-Lead Quad
Die
Plastic Gullwing
Plastic Chip Carrier
in waffle pack
HV66
HV66PG
HV66PJ
HV66X
Absolute Maximum Ratings
1
Supply voltage, V
DD
2
-0.5V to +7.0V
Output voltage, V
PP
2
-0.5V to +35V
Logic input levels
2
-0.5V to V
DD
+ 0.5V
Ground current
3
1.5A
Continuous total power dissipation
4
1200mW
Operating temperature range
-40
C to +85
C
Storage temperature range
-65
C to +125
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to V
SS
.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25
C ambient derate linearly to 85
C at 20mW/
C.
2
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
4.5
5.5
V
V
PP
Output voltage*
0
32
V
V
IH
High-level input voltage
2.4
V
DD
V
V
IL
Low-level input voltage
0
0.8
V
f
CLK
Clock frequency
0
5
MHz
T
A
Operating free-air temperature
-40
+85
C
I
OD
Allowable current through output diodes
200
mA
Notes:
*Output will not switch below 12V.
Power-up sequence should be the following:
1. Connect ground.
3.
Set all inputs (Data, CLK, Enable, etc.) to a known state.
2. Apply V
DD
.
4.
Apply V
PP
.
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operation.
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
(V
DD
= 5V, V
PP
= 32V, V
SS
= GND)
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
V
DD
= V
DD
max
f
CLK
= 5MHz
I
PPQ
High voltage supply current
0.5
mA
Outputs high
0.5
mA
Outputs low
I
DDQ
Quiescent V
DD
supply current
0.5
mA
All V
IN
= V
SS
or V
DD
V
OH
High-level output
Q
22
V
I
O
= 1mA, V
PP
= 24V
Data out
4.6
V
I
O
= -100
A
V
OL
Low-level output
Q
2
V
I
O
= 1mA
Data out
0.4
V
I
O
= 100
A
I
IH
High-level logic input current
1
A
V
IH
= V
DD
I
IL
Low-level logic input current
-1
A
V
IL
= 0V
V
OLBP
Low-level output voltage, backplane
3
V
I
O
= 10mA
V
OHBP
High-level output voltage, backplane
29
V
I
O
= -10mA
AC Characteristics
(V
DD
= 5V, V
PP
= 32V, T
C
= 25
C), logic input rises/fall time = 10ns.
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
5
MHz
t
W
Clock width high or low
100
ns
t
SU
Data set-up time before clock rises
25
ns
t
H
Data hold time after clock rises
50
ns
t
ON
, t
OFF
Time from latch enable or POL to HV
OUT
500
ns
C
L
= 20pF
t
ON
, t
OFF
Time from POL to BP output
500
ns
C
L
= 20pF
t
DHL
Delay time clock to data high to low
200
ns
C
L
= 10pF
t
DLH
Delay time clock to data low to high
200
ns
C
L
= 10pF
t
DLE
Delay time clock to LE low to high
50
ns
t
WLE
Width of LE pulse
100
ns
t
SLE
LE set-up time before clock rises
50
ns
t
BR
, t
BF
BP
OUT
rise/fall time
10
1000
s
C
L
= 350nF
t
BR
- t
BF
BP
OUT
rise and fall difference
100
s
C
L
= 350nF
Recommended Operating Conditions
HV66
3
HV66
Switching Waveforms
Latch Enable
HV
OUT
w/ S/R LOW
Data Valid
50%
50%
Data Input
Clock
Data Out
50%
50%
50%
t
SU
t
H
t
WL
t
WH
50%
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50%
HV
OUT
w/ S/R HIGH
50%
t
OFF
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
50%
t
ON
t
BR
POL
(ASYNCH
w/ Clock)
BP
OUT
V
OHBP
V
OLBP
50%
t
BF
t
ON
50%
50%
t
OFF
50%
10%
90%
50%
4
HV66
Functional Block Diagram
Inputs
Outputs
Function
Data
CLK
LE
BL
POL
DIR
Shift Reg
HV Outputs
Data Out
BP
OUT
1
2...32
1
2...32
2...32
*
Load S/R
H or L
L
H
H
X
H or L
*...*
*
*...*
*
H
Load latches
X
H or L
L
H
H
X
*
*...*
*
*...*
*
H
X
H or L
L
H
L
X
*
*...*
*
*...*
*
L
L
H
H
H
X
L
*...*
H
*...*
*
H
Transparent
H
H
H
H
X
H
*...*
L
*...*
*
H
Mode
L
H
H
L
X
L
*...*
L
*...*
*
L
H
H
H
L
X
H
*...*
H
*...*
*
L
R/L Shift
X
X
H
X
H
Qn
Qn+1
*
*...*
Q32
X
X
H
X
L
Qn
Qn-1
*
*...*
Q1
Blank
X
X
X
L
L
X
*
*...*
L
L...L
*
L
Control
X
X
X
L
H
X
*
*...*
H
H...H
*
H
Function Table
Notes:
H = high level, L = low level, X = irrelevant,
= low-to-high transition.
*
= dependent on previous stage's state before the last CLK or last LE high.
HV
OUT
1
HV
OUT
2
HV
OUT
31
HV
OUT
32
(Outputs 3 to 30
not shown)
Polarity
Blank
Latch Enable
Data Input
Clock
Data Out
32-Bit
Shift
Register
Latch
Latch
Latch
Latch
V
PP
BP
OUT
V
DD
DIR
GND
5
HV66
21
6
40
41
42
43
44
1
2
3
4
5
39 38 37 36 35 34
33
32
31
30
29
18
22
20
19
7
8
9
10
11
12 13 14 15 16 17
top view
44-pin PQFP Package
28
27
26
25
24
23
Pin Configuration
HV66
44 Pin Plastic Gullwing (QFP) Package
Pin
Function
Pin
Function
1
HV
OUT
22/11
23
Data Out
2
HV
OUT
21/12
24
GND
3
HV
OUT
20/13
25
N/C
4
HV
OUT
19/14
26
BL
5
HV
OUT
18/15
27
POL
6
HV
OUT
17/16
28
LE
7
HV
OUT
16/17
29
V
DD
8
HV
OUT
15/18
30
Clock
9
HV
OUT
14/19
31
DIR
10
HV
OUT
13/20
32
Data In
11
HV
OUT
12/21
33
V
PP
12
HV
OUT
11/22
34
BP Out
13
HV
OUT
10/23
35
HV
OUT
32/1
14
HV
OUT
9/24
36
HV
OUT
31/2
15
HV
OUT
8/25
37
HV
OUT
30/3
16
HV
OUT
7/26
38
HV
OUT
29/4
17
HV
OUT
6/27
39
HV
OUT
28/5
18
HV
OUT
5/28
40
HV
OUT
27/6
19
HV
OUT
4/29
41
HV
OUT
26/7
20
HV
OUT
3/30
42
HV
OUT
25/8
21
HV
OUT
2/31
43
HV
OUT
24/9
22
HV
OUT
1/32
44
HV
OUT
23/10
Note:
Pin designation for DIR = H/L
Example: for DIR = H, Pin 1 is HV
OUT
22
for DIR = L, Pin 1 is HV
OUT
11
Package Outline
6
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
02/06//02
2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV66
44 Pin J-Lead Package
Pin
Function
Pin
Function
1
HV
OUT
17/16
23
LE
2
HV
OUT
16/17
24
V
DD
3
HV
OUT
15/18
25
Clock
4
HV
OUT
14/19
26
DIR
5
HV
OUT
13/20
27
Data In
6
HV
OUT
12/21
28
V
PP
7
HV
OUT
11/22
29
BP Out
8
HV
OUT
10/23
30
HV
OUT
32/1
9
HV
OUT
9/24
31
HV
OUT
31/2
10
HV
OUT
8/25
32
HV
OUT
30/3
11
HV
OUT
7/26
33
HV
OUT
29/4
12
HV
OUT
6/27
34
HV
OUT
28/5
13
HV
OUT
5/28
35
HV
OUT
27/6
14
HV
OUT
4/29
36
HV
OUT
26/7
15
HV
OUT
3/30
37
HV
OUT
25/8
16
HV
OUT
2/31
38
HV
OUT
24/9
17
HV
OUT
1/32
39
HV
OUT
23/10
18
Data Out
40
HV
OUT
22/11
19
GND
41
HV
OUT
21/12
20
N/C
42
HV
OUT
20/13
21
BL
43
HV
OUT
19/14
22
POL
44
HV
OUT
18/15
Note:
1. Pin designation for DIR = H/L
Example: for DIR = H, Pin 1 = HV
OUT
17
for DIR = L, Pin 1 = HV
OUT
16
6
40
41
42
43
44
1
2
3
4
5
39 38 37 36 35 34 33 32 31 30 29
18
28
27
26
25
24
23
22
21
20
19
7
8
9
10 11 12 13 14 15 16 17
top view
44-pin PLCC
HV66
Pin Configuration
Package Outline
PDF 
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