1
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV7022-C
34-Channel Symmetric Row Driver
Device
44 J-Lead Quad
44 J-Lead Quad
Die in
44 J-Lead Quad
Ceramic Chip Carrier
Plastic Chip Carrier
waffle pack
Ceramic Chip Carrier
(MIL-Std-883 Processed*)
HV7022-C
HV7022DJ-C
HV7022PJ-C
HV7022X-C
RBHV7022DJ-C
*For Hi-Rel process flows, refer to page 5-3 of the databook.
Ordering Information
Features
Processed with HVCMOS
technology
Symmetric row drive (reduces latent imaging
in ACTFEL displays)
Output voltages up to 230V
Low-power level shifting
Source/Sink current 70mA (min.)
Shift register speed 4MHz
Pin-programmable shift direction
44-lead plastic & ceramic surface-mount packages
Hi-Rel processing available
General Description
The HV7022-C is a low-voltage serial to high-voltage parallel
converter with push-pull outputs. It is especially suited for use as
a symmetric row driver in AC thin-film electroluminescent (ACTFEL)
displays. The HV70 offers 34 output lines, a direction (DIR) pin to
give CW or CCW shift register loading, output enable (OE), and
polarity (POL) control. After DATA INPUT is entered (on the falling
edge of CLOCK), a logic high will cause the output to swing to V
PP
if POL is high, or to GND if POL is low.
Package Options
Absolute Maximum Ratings
Supply voltage, V
DD
1
-0.3V to +15V
Supply voltage, V
PP
1
-0.3V to +250V
Logic input levels
1
-0.3V to V
DD
+0.3V
Ground current
2
1.5A
Continuous total power dissipation
3
:
Plastic
1200mW
Ceramic
1500mW
Operating temperature range
Plastic
-40
C to +85
C
Ceramic
-55
C to 125
C
Storage temperature range
-65
C to +150
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25
C ambient derate linearly to maximum operating
temperature at 25mW/
C for plastic and at 15mW/
C for ceramic.
For Detailed circuit and application information, please refer
to Application Note AN-H3.
2
Electrical Characteristics
(over recommended operating conditions of V
DD
= 12V, T
A
= 25
C and V
PP
= 230V unless otherwise noted)
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
10
mA
f
CLK
= 4MHz
I
PP
High voltage supply current
4
mA
1 Output high
1
100
A
All Outputs low or High-Z
750
A
All Outputs low or High-Z
(125
C)
I
DDQ
Quiescent V
DD
supply current
100
A
All V
IN
= GND or V
DD
V
OH
High-level output
HV
OUT
195
V
I
O
= -70mA (-50mA)
2
Data out
11
V
I
O
= -500
A
V
OL
Low-level output
HV
OUT
30
V
I
O
= 70mA (+50mA)
2
Data out
1
V
I
O
= 500
A
I
IH
High-level logic input current
1
A
V
IH
= 12V
I
IL
Low-level logic input current
-1
A
V
IL
= 0V
Notes:
1. The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation.
2. Over military temperature range (-55
C to 125
C).
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
4
MHz
t
W
Pulse duration clock high or low
125
ns
t
SUD
Data set-up time before falling clock
100
ns
t
HD
Data hold time after falling clock
100
ns
t
SUC
Setup time clock low before V
PP
or GND
300
ns
t
SUE
Setup time enable high before V
PP
or GND
300
ns
t
SUP
Setup time polarity high or low before V
PP
or GND
300
ns
t
HC
Hold time clock high after V
PP
or GND
500
ns
t
HE
Hold time enable high after V
PP
or GND
300
ns
t
HP
Hold time polarity high or low after V
PP
or GND
300
ns
t
DHL
Delay time high to low level output from clock
150
ns
C
L
= 10pF
t
DLH
Delay time low to high level output from clock
200
ns
C
L
= 10pF
t
THL
Transition time high to low level serial output
200
ns
C
L
= 15pF
t
TLH
Transition time low to high level serial output
100
ns
C
L
= 15pF
t
ONH
High level turn-on time Q outputs from enable
500
ns
I
O
= -50 mA,V
OH
=195V
R
L
= 2 k
to 95V
t
ONL
Low level turn-on time Q outputs from enable
500
ns
I
O
= 50 mA,V
OH
=130V
R
L
= 2 k
to 30V
t
OFFH
High level turn-off time Q outputs from enable
1000
ns
I
O
= -50 mA,V
OH
=195V
R
L
= 2 k
to 95V
t
OFFL
Low level turn-off time Q outputs from enable
500
ns
I
O
= 50 mA,V
OH
=130V
R
L
= 2 k
to 30V
Slew rate, V
PP
or GND
45
V/
s
With one active output
driving a 4.7 nF load to
V
PP
or GND
AC Characteristics
(V
DD
= 12V, T
C
= 25
C)
HV7022-C
3
HV7022-C
V
DD
Input
GND
V
PP
GND
HV
OUT
Logic Inputs
GND
Data Out
Logic Data Output
High Voltage Outputs
V
DD
Recommended Operating Conditions
Input and Output Equivalent Circuits
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
10.8
13.2
V
V
PP
High voltage supply
230
V
V
IH
High-level input voltage
V
DD
= 10.8V
8.1
V
V
DD
= 13.2V
9.9
V
IL
Low-level input voltage
V
DD
= 10.8V
2.7
V
V
DD
= 13.2V
3.3
f
CLK
Clock frequency
4
MHz
T
A
Operating free-air temperature
Plastic
-40
+85
C
Ceramic
-55
+125
C
I
OD
Allowable pulse current through output diodes
300
mA
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
4
HV7022-C
50%
50%
Data Output
(D
IOA
/D
IOB
)
Clock
50%
50%
50%
t
SUD
t
HD
V
IH
t
WL
t
WH
l/f
CLK
t
TLH
90%
10%
t
THL
90%
10%
t
DLH
t
DHL
Data Input
V
IH
V
IL
V
OH
V
OL
t
SUC
10%
90%
t
HC
V
PP
GND
50%
50%
V
IH
V
IL
90%
POL
GND
10%
t
SUP
t
HP
50%
50%
t
SUE
t
HE
10%
90%
10%
90%
t
ONL
t
ONH
t
OFFL
t
OFFH
V
IH
V
IL
V
OH
V
OL
V
PP
OE
HV
OUT
HV
OUT
High Impedance
High Impedance
Switching Waveforms
5
HV7022-C
HV
OUT
1
OE
Polarity
Data In
Data Out
GND
S/R
CLK
V
DD
V
PP
DIR
HV
OUT
2
HV
OUT
34
LT
LT
LT
LT = Level Translator
P
N
Notes:
H = logic high level, L = logic low level, X = irrelevant,
= high-to-low transition,
Q
1
= HV
OUT
1, Q
n
= HV
OUT
(n), etc.
* = dependent on previous state and whether an O/P or S/R command occured.
Inputs
Outputs
I/O
Relations
Shift Reg
HV Outputs
Data Out
O/P HIGH
X
X
H
H
H
*
H
O/P OFF
X
X
L
H
H
*
HIGH-Z
*
O/P LOW
X
X
H
L
H
*
L
*
O/P OFF
X
X
L
L
H
*
HIGH-Z
*
O/P OFF
X
X
X
X
L
*
All O/P HIGH-Z
*
L
X
X
X
Q
n
Q
n+1
*
Q
34
H
X
X
X
Q
n
Q
n-1
*
Q
1
No
X
X
X
X
*
No Change
No Change
Functional Block Diagram
Function Table
CLK
DIR
Data
POL
OE
Load S/R,
set DIR
6
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
02/06//02
2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV7022-C
I
(mA)
I
(mA)
Volts
0
20
40
60
80
180
140
100
60
20
0
100
20
40
60
80
V
PP
> 40V
V
DD
= 12V & 14 V
100
180
140
100
60
20
Volts (V
PP
- V
OUT
)
Temp = 25 C
Temp = 25 C
V
DD
= 14
V
DD
= 10
V
DD
= 12
HV
OUT
Characteristics
Output N-Channel Characteristics through FET
Output P-Channel Characteristics through FET
Pin Configurations
Package Outline
HV70
44 Pin J-Lead Package
Pin
Function
Pin
Function
1
HV
OUT
18/17
23
DIR
2
HV
OUT
17/18
24
V
DD
3
HV
OUT
16/19
25
Polarity
4
HV
OUT
15/20
26
Data In
5
HV
OUT
14/21
27
V
PP
6
HV
OUT
13/22
28
N/C
7
HV
OUT
12/23
29
HV
OUT
34/1
8
HV
OUT
11/24
30
HV
OUT
33/2
9
HV
OUT
10/25
31
HV
OUT
32/3
10
HV
OUT
9/26
32
HV
OUT
31/4
11
HV
OUT
8/27
33
HV
OUT
30/5
12
HV
OUT
7/28
34
HV
OUT
29/6
13
HV
OUT
6/29
35
HV
OUT
28/7
14
HV
OUT
5/30
36
HV
OUT
27/8
15
HV
OUT
4/31
37
HV
OUT
26/9
16
HV
OUT
3/32
38
HV
OUT
25/10
17
HV
OUT
2/33
39
HV
OUT
24/11
18
HV
OUT
1/34
40
HV
OUT
23/12
19
Data Out
41
HV
OUT
22/13
20
Output Enable
42
HV
OUT
21/14
21
Clock
43
HV
OUT
20/15
22
GND
44
HV
OUT
19/16
Note:
Pin designation for DIR L/H
Example:For DIR = L, pin 1 is HV
OUT
18
For DIR = H, pin 1 is HV
OUT
17
6
40
41
42
43
44
1
2
3
4
5
39 38 37 36 35 34 33 32 31 30 29
18
28
27
26
25
24
23
22
21
20
19
7
8
9
10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
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