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02/96/022
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Device
80-Lead
64-Lead 3-Sided
Die in waffle pack
80-Lead
Ceramic Gullwing
Plastic Gullwing
Ceramic Gullwing
(MIL-STD-883 Processed*)
HV7224
HV7224DG
HV7224PG
HV7224X
RBHV7224DG
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
HV7224
40-Channel Symmetric Row Driver
Ordering Information
Package Options
General Description
The HV72 is a low-voltage serial to high-voltage parallel convert-
ers with push-pull outputs. It is especially suitable for use as a
symmetric row driver in AC thin-film electroluminescent (ACTFEL)
displays.
When the data reset pin (DR
IO
) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR
IO
can be
triggered at any time. The DIR and SHIFT pins control the
direction of data shift through the device. When DIR is at logic
high, DR
IOA
is the input and DR
IOB
is the output. When DIR is
grounded, DR
IOB
is the input and the DR
IOA
is the output. See the
Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to V
PP
if
POL is high, or to GND if POL is low. All outputs will be in High-
Z state if OE is at logic high. Data output buffers are provided for
cascading devices.
Features
Processed with HVCMOS
technology
Symmetric row drive (reduces latent imaging
in ACTFEL displays)
Output voltage up to 240V
Low-power level shifting
Source/Sink current 70mA (min.)
Shift Register Speed 3MHz
Pin-programmable shift direction (DIR, SHIFT)
Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, V
DD
1
-0.5V to +7V
Supply voltage, V
PP
-0.5V to +260V
Logic input levels
-0.5V to V
DD
+0.5V
Continuous total power dissipation
2
Plastic
1200mW
Ceramic
1900mW
Operating temperature range
Plastic
-40
C to +85
C
Ceramic -55
C to +125
C
Storage temperature range
-65
C to +150
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. For operation above 25
C ambient derate linearly to maximum operating tem-
perature at 20mW/
C for plastic and at 19mW/
C for ceramic.
2
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
10
mA
f
CLK
= 3MHz
I
PP
High voltage supply current
2.0
mA
Outputs low or High-Z
4.0
mA
One Output High
1
I
DDQ
Quiescent V
DD
supply current
100
A
All V
IN
= GND or V
DD
V
OH
High-level output
HV
OUT
190
V
I
O
= -70mA
Data out
4.5
V
I
O
= -100
A
V
OL
Low-level output
HV
OUT
50
V
I
O
= 70mA
Data out
0.5
V
I
O
= 100
A
I
IH
High-level logic input current
1.0
A
V
IH
= V
DD
I
IL
Low-level logic input current
-1.0
A
V
IL
= 0V
I
SAT
Saturation current HV
OUT
P-Ch
-80
mA
N-Ch
75
mA
Note:
1. Only one output can be turned on at a time.
Electrical Characteristics
(over recommended operating conditions of V
DD
= 5V, V
PP
= 240V, and T
A
= 25
C unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
3.0
MHz
t
W (H/L)
Pulse width - clock high or low
150
ns
t
SUD
Data set-up time before clock rises
50
ns
t
HD
Data hold time after clock rises
50
ns
t
SUC
HV
OUT
delay from clock rises (Hi-Z to H or L)
1.0
s
C
L
= 330pF // R
L
= 10k
t
SUE
HV
OUT
delay from Output Enable falls
600
ns
C
L
= 330pF // R
L
= 10k
t
HC
HV
OUT
delay from clock rises (H or L to Hi-Z)
2.0
s
C
L
= 330pF // R
L
= 10k
t
HE
HV
OUT
delay from Output Enable rises
600
ns
C
L
= 330pF // R
L
= 10k
t
DHL
*
Delay time clock to data output falls
250
ns
C
L
= 15pF
t
DLH
*
Delay time clock to data output rises
250
ns
C
L
= 15pF
t
ONF
HV
OUT
fall time
2.0
s
C
L
= 330pF // R
L
= 10k
t
ONR
HV
OUT
rise time
2.0
s
C
L
= 330pF // R
L
= 10k
t
POW
POL pulse width
3.0
s
t
OEW
Output Enable pulse width
3.0
s
Slew rate, V
PP
or GND
45
V/
s
One active output driving
4.7nF load
AC Characteristics
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
. Therefore the delay is measured from the trailing edge of the clock.
HV7224
3
HV7224
V
DD
Input
GND
(Logic)
V
PP
GND
(Power)
HV
OUT
Logic Inputs
GND
(Logic)
Data Out
Logic Data Output
High Voltage Outputs
V
DD
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
4.5
5.5
V
V
PP
High voltage supply
0
240
V
V
IH
High-level input voltage
0.7 V
DD
V
DD
V
V
IL
Low-level input voltage
0
0.2V
DD
V
f
CLK
Clock frequency
3
MHz
I
O
High voltage output current
70
mA
T
A
Operating free-air temperature
Plastic
-40
+85
C
Ceramic
-55
+125
C
I
OD
Allowable pulse current through output diode
300
mA
Notes:
Output will not switch at V
PP
= 0V.
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Recommended Operating Conditions
Input and Output Equivalent Circuits
4
HV7224
Switching Waveforms
Data Reset Input
(DR
IOA
/DR
IOB
)
50%
50%
t
POW
Data Reset Output
(DR
IOA
/DR
IOB
)
t
HD
50%
50%
V
IH
V
IL
High Impedance
90%
10%
10%
HV
OUT
HV
OUT
90%
t
SUE
t
ONR
90%
t
HE
10%
50%
t
DLH
50%
t
DHL
50%
t
OEW
50%
High Impedance
High Impedance
High Impedance
90%
10%
10%
90%
t
SUC
t
ONR
90%
t
HC
10%
HV
OUT
(POL = H)
HV
OUT
(POL = L)
POL
OE
Data
Valid
t
SUD
Data
Valid
CLK
t
WL
l/f
CLK
50%
50%
50%
50%
t
WH
t
SUC
t
ONF
t
HC
t
SUE
t
ONF
t
HE
V
IH
V
IL
V
OH
V
OH
V
OL
V
IH
V
IL
V
OL
V
IH
V
IL
V
OH
V
OL
5
HV7224
DIR
Shift
Data Reset In Data Reset Out
HV
OUT
# Sequence
Direction*
Option (See pin-out on P. 12-158)
L
L
DR
IOB
DR
IOA
1
40
1
A
H
L
DR
IOA
DR
IOB
2
1
40
A
L
H
DR
IOB
DR
IOA
1
20
1
40
21
B
H
H
DR
IOA
DR
IOB
2
21
40
1
20
B
Functional Block Diagram
I/O Relations
Inputs
CLK
DIR
S/R Data
POL
OE
HV Outputs
O/P HIGH
X
X
H
H
L
H
O/P OFF
X
X
L
X
L
HIGH-Z
O/P LOW
X
X
H
L
L
L
O/P OFF
X
X
X
X
H
All O/P HIGH-Z
Function Table
* Reference to package outline or chip layout drawing.
1.DR
IOA
is DR
IOB
delayed by 40 clock pulses.
2. DR
IOB
is DR
IOA
delayed by 40 clock pulses.
Output Sequence Operation Table
Notes
:
H = logic high level, L = logic low level, X = irrelevant
Data input (DR
IO
) loaded on the low-to-high transistion of the clock.
Only one active output can be set at a time.
HV
OUT
1
HV
OUT
2
HV
OUT
40
OE
CLK
S/R
DIR
Polarity
SHIFT
P
LT
N
LT
LT
GND
LT = Level Translator
V
DD
V
PP
D
IOA
D
IOB
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