TC6320

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Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate
"products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices
determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For
the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or
to the Legal/Disclaimer page on the Supertex website.

Initial Release

N- and P-Channel Enhancement-Mode MOSFET Pair

Features

Integrated gate-source resistor

Integrated gate-source zener diode

Low threshold

Low on-resistance

Independent N- and P-channels

Electrically isolated N- and P-channels

Low input capacitance

Fast switching speeds

Free from secondary breakdowns

Low input and output leakage

Application

High voltage pulsers

Amplifiers

Buffers

Piezoelectric transducer drivers

General purpose line drivers

Logic level interfaces

Absolute Maximum Ratings*

Drain-to-Source Voltage

DSS

Drain-to-Gate Voltage

DGS

Operating and Storage Temperature

-55癈 to +150癈

Soldering Temperature*

300癈

*Distance of 1.6mm from case for 10 seconds.

General Description

The Supertex TC6320TG consists of a high voltage low
threshold N-channel and P-channel MOSFET in an SO-8
package. Both MOSFETs have integrated gate-source
resistors and gate-source zener diode clamps which are
desired for high voltage pulser applications. TC6320TG, a
complementary high-speed, high voltage, gate-clamped
N- and P-channel MOSFET pair in a single SO-8
package. The TC6320TG offers 200V breakdown voltage,
2.0A output peak current and low input capacitance. The
2.0A output current capability will minimize rise and fall
times. The low input capacitance will minimize
propagation delay times and also rise and fall times. The
MOSFETs have integrated gate-source resistors and
gate-source zener diode clamps that are desired for high
voltage pulser applications saving board space and
improving performance. It is specifically designed for
applications in medical ultrasound transmitters and non-
destructive evaluation in materials flaw detection, but it
can also be used as an efficient buffer.

Package Option

SO-8 Package

(top view)

N-Channel

P-Channel

TC6320

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Supertex, Inc. January 21, 2003

DSS

/ BV

DGS

DS(ON)

(max)

Order Number / Package

N-Channel P-Channel N-Channel P-Channel

SO-8

200V -200V 7.0

8.0

TC6320TG

N-Channel Electrical Characteristics

(at T

=25癈 unless otherwise specified)

Symbol Parameter

Min Typ Max Units Conditions

DSS

Drain-to-Source

Breakdown Voltage

200 V V

=0V, I

=2mA

GS(th)

Gate Threshold Voltage

1.0

2.0

, I

=1mA

GS(th)

Change in V

GS(th)

with Temperature

-4.5

mV/癈 V

, I

=1mA

Gate-Source Shunt Resistor

=100礎

Change in R

with Temperature

TBD

%/癈

=100礎

Gate-Source Zener Voltage

13.2

=2mA

Change in Vz

with Temperature

TBD

mV/癈 I

=2mA

礎

=0V, V

=Max Rating

DSS

Zero Gate Voltage Drain Current

1.0

=0V, V

=0.8 Max

Rating, T

=125癈

1.0

=4.5V, V

=25V

D(ON)

On-State Drain Current

2.0

=10V, V

=25V

8.0

=4.5V, I

=150mA

DS(ON)

Static

Drain-to-Source

ON-State Resistance

7.0

=10V, I

=1.0A

DS(ON)

Change in R

DS(ON)

with Temperature

1.0

%/癈

=4.5V, I

=150mA

Forward

Transconductance

400

mmho

=25V, I

=200mA

ISS

Input

Capacitance

110

OSS

Common Source Output Capacitance

RSS

Reverse Transfer Capacitance

=0V, V

=25V

f=1MHz

d(ON)

Turn-ON Delay Time

Rise

Time

d(OFF)

Turn-Off Delay Time

Fall

Time

=25V,

=1.0A

GEN

=25

Diode Forward Voltage Drop

1.8

=0V, I

=0.5A

Reverse Recovery Time

300

=0V, I

=0.5A

Notes:
1) All DC parameters 100% tested at 25癈 unless otherwise stated. (Pulsed test: 300祍 pulse at 2% duty cycle.)
2) All AC parameters sample tested.

N-Channel Switching Waveforms and Test Circuit

GEN

Input

Pulse

Generator

D.U.T

OUTPUT

10V

d(OFF)

Input

Output

d(ON)

(ON)

(OFF)

10%

90%

10%

90%

10%

TC6320

________________________________________________________________________________

P-Channel Electrical Characteristics

(at T

=25癈 unless otherwise specified)

Symbol Parameter

Min Typ Max Units Conditions

DSS

Drain-to-Source

Breakdown Voltage

-200 V V

=0V, I

=-2mA

GS(th)

Gate Threshold Voltage

-1.0

-2.4

, I

=-1mA

GS(th)

Change in V

GS(th)

with Temperature

4.5

mV/癈 V

, I

=-1mA

Gate-Source Shunt Resistor

=-100礎

Change in R

with Temperature

TBD

%/癈

=-100礎

Gate-Source Zener Voltage

13.2

=-2mA

GS(th)

Change in Vz

with Temperature

TBD

mV/癈 I

=-2mA

-10

礎

=0V, V

=Max Rating

DSS

Zero Gate Voltage Drain Current

-1.0

=0V, V

=0.8 Max

Rating, T

=125癈

-1.0

=-4.5V, V

=-25V

D(ON)

On-State Drain Current

-2.0

=-10V, V

=-25V

=-4.5V, I

=-150mA

DS(ON)

Static

Drain-to-Source

ON-State Resistance

8.0

=-10V, I

=-1.0A

DS(ON)

Change in R

DS(ON)

with Temperature

1.0

%/癈

=-10V, I

=-200mA

Forward

Transconductance

400

mmho

=-25V, I

=-200mA

ISS

Input

Capacitance

200

OSS

Common Source Output Capacitance

RSS

Reverse Transfer Capacitance

=0V, V

=-25V

f=1MHz

d(ON)

Turn-ON Delay Time

Rise

Time

d(OFF)

Turn-Off Delay Time

Fall

Time

=-25V,

=-1.0A

GEN

=25

Diode Forward Voltage Drop

-1.8

=0V, I

=-0.5A

Reverse Recovery Time

300

=0V, I

=-0.5A

Notes:
1) All DC parameters 100% tested at 25癈 unless otherwise stated. (Pulsed test: 300祍 pulse at 2% duty cycle.)
2) All AC parameters sample tested.

P-Channel Switching Waveforms and Test Circuit

GEN

Input

Pulse

Generator

D.U.T

OUTPUT

-10V

d(OFF)

Input

Output

d(ON)

(ON)

(OFF)

90%

10%

90%

10%

90%

1/22/03

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: TC6320TG

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: TC6320TG