TSL1412S
1536
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS045 SEPTEMBER 2002
1
The
LUMENOLOGY
r
Company
t
t
Copyright
E
2002, TAOS Inc.
www.taosinc.com
D
1536
1 Sensor-Element Organization
D
400 Dot-Per-Inch (DPI) Sensor Pitch
D
High Linearity and Uniformity
D
Wide Dynamic Range . . . 4000:1 (72 dB)
D
Output Referenced to Ground
D
Low Image Lag . . . 0.5% Typ
D
Operation to 8 MHz
D
Single 3-V to 5-V Supply
D
Rail-to-Rail Output Swing (AO)
D
No External Load Resistor Required
Description
The TSL1412S linear sensor array consists of 2
sections of 768 photodiodes, each with
associated charge amplifier circuitry, aligned to
form a contiguous 1536
1 pixel array. The device
incorporates a pixel data-hold function that
provides simultaneous-integration start and stop
times for all pixels. The pixels measure 63.5
m by
55.5
m with 63.5-
m center-to-center spacing
and 8-
m spacing between pixels. Operation is
simplified by internal logic that requires only a
serial-input (SI) pulse and a clock.
The device is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section)
2,8
4,10
SI
CLK
768-Bit Shift Register (2 each)
Q768 (Q1536)
Switch Control Logic
Integrator
Reset
_
+
Pixel 1 (769)
Pixel
2
(770)
Pixel
768
(1536)
Pixel
3
(771)
Sample/
Output
Analog
Bus
Q3
Q2
Q1
Hold
SO
7, 11
3, 9
Hold
5
13
6, 12
Output
Buffer
Gain
Trim
V
DD
AO
GND
t
t
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205
S
Plano, TX 75074
S
(972) 673-0759
(TOP VIEW)
V
PP
SI1
HOLD1
CLK1
GND
AO1
SO1
SI2
HOLD2
CLK2
SO2
AO2
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
TSL1412S
1536
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS045 SEPTEMBER 2002
2
t
t
Copyright
E
2002, TAOS Inc.
The
LUMENOLOGY
r
Company
www.taosinc.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AO1
6
O
Analog output, section 1.
AO2
12
O
Analog output, section 2.
CLK1
4
I
Clock, section 1. CLK1 controls charge transfer, pixel output, and reset.
CLK2
10
I
Clock, section 2. CLK2 controls charge transfer, pixel output, and reset.
GND
5
Ground (substrate). All voltages are referenced to GND.
HOLD1
3
I
Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in
serial mode and to SI1 in parallel mode.
HOLD2
9
I
Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode.
SI1
2
I
Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2
8
I
Serial input (section 2). SI2 defines the start of the data-out sequence.
SO1
7
O
Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode.
SO2
11
O
Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an
end-of-data indication.
V
DD
13
Supply voltage for both analog and digital circuitry.
V
PP
1
Normally grounded.
Detailed Description
The sensor consists of 1536 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel
generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The
amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time.
The output and reset of the integrators are controlled by a 768-bit shift register and reset logic. An output cycle is initiated
by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1
are connected together. This causes all 768 sampling capacitors to be disconnected from their respective integrators and
starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling
capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO.
The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins.
On the 768th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section
2 (when SO1 is connected to SI2). The rising edge of the 769th clock cycle terminates the SO1 pulse, and returns the analog
output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1536th clock pulse. Note that a 1537th
clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. Sections may
be operated in parallel or in serial fashion.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing.
With V
DD
= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level.
When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
V
out
= V
drk
+ (R
e
) (E
e
)(t
int
)
where:
V
out
is the analog output voltage for white condition
V
drk
is the analog output voltage for dark condition
R
e
is the device responsivity for a given wavelength of light given in V/(
J/cm
2
)
E
e
is the incident irradiance in
W/cm
2
t
int
is integration time in seconds
A 0.1
F bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
TSL1412S
1536
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS045 SEPTEMBER 2002
3
The
LUMENOLOGY
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Company
t
t
Copyright
E
2002, TAOS Inc.
www.taosinc.com
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
DD
0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.3 V to V
DD
+ 0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) or (V
I
> V
DD
)
20 mA to 20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
)
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high impedance or power-off state, V
O
0.3 V to V
DD
+ 0.3 V
. . .
Continuous output current, I
O
(V
O
= 0 to V
DD
)
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
DD
or GND
40 mA to 40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog output current range, I
O
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum light exposure at 638 nm
5 mJ/cm
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
25
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply voltage, V
DD
3
5
5.5
V
Input voltage, V
I
0
V
DD
V
High-level input voltage, V
IH
V
DD
0.7
V
DD
V
Low-level input voltage, V
IL
0
V
DD
0.3
V
Wavelength of light source,
400
1100
nm
Clock frequency, f
clock
5
8000
kHz
Sensor integration time, Serial, t
int
0.194
100
ms
Sensor integration time, Parallel, t
int
0.098
100
ms
Setup time, serial input, t
su(SI)
20
ns
Hold time, serial input, t
h(SI)
(see Note 1)
0
ns
Operating free-air temperature, T
A
0
70
C
Load capacitance, C
L
330
pF
Load resistance, R
L
300
NOTE 1: SI must go low before the rising edge of the next clock pulse.
TSL1412S
1536
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS045 SEPTEMBER 2002
4
t
t
Copyright
E
2002, TAOS Inc.
The
LUMENOLOGY
r
Company
www.taosinc.com
Electrical Characteristics at f
clock
= 1 MHz, V
DD
= 5 V, T
A
= 25
C,
p
= 640 nm, t
int
= 5 ms,
R
L
= 330
, E
e
= 12.5
W/cm
2
(unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
out
Analog output voltage (white, average over 1280 pixels)
See Note 3
1.6
2
2.4
V
V
drk
Analog output voltage (dark, average over 1280 pixels)
E
e
= 0
0
0.1
0.3
V
PRNU
Pixel response nonuniformity
See Note 4
20%
Nonlinearity of analog output voltage
See Note 5
0.4%
Output noise voltage
See Note 6
1
mVrms
R
e
Responsivity
See Note 7
78
112
V/
(
J/cm
2
)
V
Analog output saturation voltage
V
DD
= 5 V, R
L
= 330
4.5
4.8
V
V
sat
Analog output saturation voltage
V
DD
= 3 V, R
L
= 330
2.5
2.8
V
SE
Saturation exposure
V
DD
= 5 V, See Note 8
155
nJ/cm
2
SE
Saturation exposure
V
DD
= 3 V, See Note 8
90
nJ/cm
2
DSNU
Dark signal nonuniformity
All pixels, E
e
= 0, See Note 9
0.05
0.15
V
IL
Image lag
See Note 10
0.5%
I
Supply current
V
DD
= 5 V, E
e
= 0
40
55
mA
I
DD
Supply current
V
DD
= 3 V, E
e
= 0
30
45
mA
V
IH
High-level input voltage
2
V
V
IL
Low-level input voltage
0.8
V
I
IH
High-level input current
V
I
= V
DD
10
A
I
IL
Low-level input current
V
I
= 0
10
A
C
i
Input capacitance, SI
25
pF
C
i
Input capacitance, CLK
25
pF
NOTES: 2. All measurements made with a 0.1
F capacitor connected between V
DD
and ground.
3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. R
e(min)
= [V
out(min)
V
drk(max)
]
(E
e
t
int
)
8. SE(min) = [V
sat(min)
V
drk(min)
]
E
e
t
int
)
[V
out(max)
V
drk(min)
]
9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
V
out (IL)
*
V
drk
V
out (white)
*
V
drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
t
su(SI)
Setup time, serial input (see Note 11)
20
ns
t
h(SI)
Hold time, serial input (see Note 11 and Note 12)
0
ns
t
pd(SO)
Propagation delay time, SO
50
ns
t
w
Pulse duration, clock high or low
50
ns
t
r
, t
f
Input transition (rise and fall) time
0
500
ns
NOTES: 11. Input pulses have the following characteristics: t
r
= 6 ns, t
f
= 6 ns.
12. SI must go low before the rising edge of the next clock pulse.
TSL1412S
1536
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS045 SEPTEMBER 2002
5
The
LUMENOLOGY
r
Company
t
t
Copyright
E
2002, TAOS Inc.
www.taosinc.com
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 7 and 8)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
s
Analog output settling time to
1%
R
L
= 330
,
C
L
= 50 pF
120
ns
t
pd(SO)
Propagation delay time, SO1, SO2
50
ns
TYPICAL CHARACTERISTICS
18 Clock Cycles
Not Integrating
Integrating
1537 Clock Cycles
Hi-Z
Hi-Z
CLK
SI1
Internal
Reset
Integration
AO
tint
Figure 1. Timing Waveforms (serial connection)
AO
SI
CLK
Pixel 768
t
s
t
h(SI)
t
su(SI)
t
w
1
2
768
769
Pixel 1
SO
t
pd(SO)
t
pd(SO)
50%
0 V
0 V
5 V
5 V
2.5 V
Figure 2. Operational Waveforms (Each Section)
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