78P7200L
E3/DS3/STS-1
Transceiver
March 2001
DESCRIPTION
The 78P7200L is a line interface transceiver IC for
E3, DS3, STS-1, North America T3 and ATM
applications. It includes clock recovery and
transmitter pulse shaping functions for applications
using 75-ohm coaxial cable at distances up to 1100
feet. These applications include DSLAMs, T3/E3
digital multiplexers, SONET Add/Drop multiplexers,
PDH equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
The receiver recovers clock and positive data and
negative data from an AMI signal. It can compensate
for over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
The 78P7200L is pin and functionally compatible to
the 78P7200. It adds loop-back and clock polarity
selection.
The 78P7200L is manufactured in an advanced
BICMOS process and operates at both 5V and
3.3 V power supply voltages. It consumes less than
95 mA of supply current.
FEATURES
Single chip transmit and receive interface for
E3, DS3 and STS-1 applications.
Interface to 75 ohm coaxial cable over 1100
feet at speeds up to 51.84 Mbps.
Compliant with ANSI T1.102-1993, Telcordia
GR-499-CORE and GR-253-CORE, ITU-T
G.703 and G.823 for jitter tolerance.
Compliant with ATM FORUM af-phy-0034 (E3
public UNI) and af-phy-0054 (DS3 public UNI).
Easily Interfaced to ATM framer ICs such as
PMC 7345 , 7346 QJET and 7321.
Unique clock recovery requires no reference
clock or crystal oscillator.
Receive DS3-high signal
Includes diagnostic loop-back for AMI and digital
signals.
Pin compatible to 78P7200 and 78P2241 (28-
lead PLCC).
28-lead PLCC and 48-lead TQFP packages
3.3 or 5 V operation, ICC<95mA
Input circuit works either Transformer or
Capacitor coupled
BLOCK DIAGRAM
PULSE
SHAPER
Clock
Recovery
Adaptive
Equalizer
Data
Slicer
LOS
LINN
LINP
LOUTN
LOUTP
TPOS
LPBK
LF
Signal
Detector
TNEG
AMI
to
Binary
Binary
to
AMI
TCLK
RCLK
RPOS
RNEG
Biasing
RFO
LPBK
LBO
TXEN
TDK SEMICONDUCTOR CORP.
78P7200L
E3/DS3/STS-1
Transceiver
2
FUNCTIONAL DESCRIPTION
The 78P7200L is a single chip line interface IC
designed to work with a 51.84 Mbit/s STS-1, 44.736
Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver
recovers clock, positive data and negative data from
an Alternate Mark Inversion (AMI) signal. The AMI
line input signal should be B3ZS or HDB3 coded.
The transmitter accepts clock, positive, and negative
data and converts them into an AMI signal to drive a
75
coaxial cable. The shape of the transmitted
signal though any cable length of 0 to 450 feet complies
with the published templates of ANSI T1.102-1993,
Telcordia TR-NWT-000499 and GR-253-CORE, ITU-T
G.703. The 78P7200L is designed to work with B3ZS
or HDB3 coded signals. The B3ZS or HDB3 encoding
and decoding functions can be included in the framer
ICs. The 78P7200L is designed to easily connect to
popular ATM framer ICs such as PMC 7345 (SUNI-
PDH), PMC 7346 (QJET) and 7321.
OPERATION SPEED
Internal bias generators that are adjusted by the value of
the RFO set the 78P7200L PLL center frequency and
Transmitter amplitude for the different standards. The
E#
pin controls the equalizer response and the transmitter
pulse shape and amplitude. The following table shows
the proper settings.
STANDARD
RFO VALUE,
K
E#
E#
E#
E# PIN SETTING
E3 6.81 Low
DS3 5.23
High
STS-1 4.53
Float
RECEIVER
The receiver input can be either transformer-coupled
or capacitor coupled to the AMI signal. In
applications where the highest performance and
isolation is required, a 1:1 transformer is used on the
receiver path. In the applications, where isolation is
provided elsewhere in the circuit, an AC coupling
can be used. The inputs to the IC are internally
referenced to Vcc. Since the input impedance of the
78P7200L is high, the AMI line must be terminated
to 75
. The input signal of the 78P7200L must be
limited to a maximum of three consecutive zeros
using a coding scheme such as B3ZS or HDB3.
The AMI signal first enters an equalizer and AGC
gain stage. The equalizer is designed to overcome
intersymbol interference caused by long cables.
Because the equalizer is adaptive, the circuit will work
with all square shaped signals such as DS3 high or 34
Mbit/s E3. The variable gain differential amplifier
maintains a constant voltage level output regardless
of the input voltage level. The gain of the amplifier is
adjusted by detecting the peak of the signal and
comparing it to a fixed reference.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a phase locked loop with an
auxiliary frequency-sensitive acquisition loop. This
system permits the loop to independently lock to the
frequency and phase of the incoming data stream
without the need for an external, high precision
tuned circuits or reference clock signal.
The jitter tolerance of the 78P7200L meets the
requirements of Telcordia GR-499-CORE for
Category I equipment for DS3 rates and exceeds the
requirements of ITU-T G.823 for E3 rates.
78P7200L
E3/DS3/STS-1
Transceiver
3
FUNCTIONAL DESCRIPTION
(continued)
LOSS OF SIGNAL
Should the input signal fall below a minimum value,
the loss of signal indication,
LOS goes low.
TRANSMITTER
The transmitter accepts logic level clock (TCLK),
positive data (TPOS) and negative data (TNEG)
signals and generates current pulses on the LOUT+
and LOUT- pins. When properly connected to a
center-tapped 1:2 transformer, an AMI pulse is
generated which can drive a 75
coaxial cable.
When the recommended transformer is used and the
E# pin is set high, the transmitted pulse shape at the
end of the 75
terminated cable of 0 to 450 feet will
fit the DS3 template in ANSI T1.102-1993 and
Telcordia GR-499-CORE standard documents.
For STS-1 applications, the transmitted pulse for a
short cable meets the requirements of TelcordiaGR-
253-CORE. The
E# pin should be allowed to float.
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703. The
E# pin is to be pulled low.
RCLK/TCLK POLARITY REVERSAL:
To simplify the interface with framer circuitry, RCLK
and TCLK can be inverted with the ICKP pin.
PIN 10
ICKP
RCLK TCLK
Low Normal
Normal
Float Invert
Invert
High Normal
Invert
LOOP-BACK MODES:
The following loop-back modes allow for the
diagnostic test of the PC board. This function is
controlled by the
LPBK pin.
PIN 40/TQFP
PIN 28/PLCC
LPBK
LPBK
LPBK
LPBK
LOOP-BACK
Low
Local loop-back (LLB)
Float
Remote loop-back (RLB)
High Normal
Operation
LOCAL LOOP-BACK:
When
LPBK is low, the 78P7200L enters Local
loopback. In this mode, the LOUT+/- transmit signals
are internally routed to the receiver input circuit. The
incoming line receiver AMI signal on LIN+/- is
ignored. With the transmitter still tied to the cable,
this test mode can indicate a short circuit on the
transmitter external components or other problem in
the transmit path.
REMOTE LOOP-BACK:
When
LPBK pin is allowed to float, the 78P7200L
enters remote loopback mode. The RPOS/RNEG
and RCLK pins are internally tied to the
TPOS/TNEG and TCLK so the same AMI signal that
is received by the framer is transmitted back to the
far end where a bit continuity test can be performed.
LINE BUILD-OUT:
The Line Build-Out function controls the amplitude in
DS3 and STS-1 mode. The selection of LBO
depends on the amount of cable the transmitter is
connected to. When used with less than 225 ft of
cable the LBO pin should be pulled high. With 225ft
or more cable the LBO pin should be low.
78P7200L
E3/DS3/STS-1
Transceiver
4
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241
NAME
PIN
TQFP
PIN
PLCC
TYPE DESCRIPTION
LIN+
LIN-
42
44
1
3
I
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
RCLK
33
23
O
Receive Clock: Recovered receive clock.
RPOS/
RNRZ
35
25
O
Receive Positive Data / NRZ Data: This pin indicates
reception of a positive AMI pulse on the coax cable.
RNEG 34 24
O
Receive Negative Data: This pin indicates reception of a
negative AMI pulse on the coax.
LOS
39
27
O
Loss of Signal: logic low indicates that receiver signal
(LIN) is below the threshold level
RPOS and RNEG are forced low when
LOS=0.
LOUT+
LOUT-
9
11
9
11
O
Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301
resistor.
TCLK
18
16
I
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P7200L.
TPOS/
TNRZ
16 14
I
Transmit Positive Data / Transmit NRZ: A logic one on this
pin generates a positive AMI pulse on the coax. This pin
should not be high at the same time that TNEG is high.
TNEG 17 15
I
Transmit Negative Data: A logic one on this pin generates
a negative AMI pulse on the coax. This pin should not be
high at the same time that TPOS/TNRZ is high.
LBO
13
12
I
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used
with less than 225ft of cable.
E#
15 13
I3
DS3, E3 and STS-1 Select:
Set low for E# applications.
Set high for DS3, allow to float for STS-1 operation.
Formerly
OPT! on the 78P7200.
TXEN
22
18
I
Transmitter Enable: When high, enables transmitter.
When low, tri-states transmitter drivers, LOUT. This pin
was called
OPT@ on 78P7200.
ICKP
10
10
I3
Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set
high, the polarity of TCLK is inverted. When allowed to float,
the polarities of both RCLK and TCLK are inverted.
LPBK
40
28
I3
Loop-back Select: When high, neither loop-back is
activated.
When allowed to float RPOS, RNEG and RCLK are
looped back onto TPOS, TNEG and TCLK. When low,
LOUT is looped back onto LIN.
VCC 5,6,20,
21,37,38
7,17,26 P
Power
Supply.
N/C
27, 28
20, 21
No Connect
78P7200L
E3/DS3/STS-1
Transceiver
5
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241(continued)
NAME
PIN
TQFP
PIN
PLCC
TYPE DESCRIPTION
GND
1, 3, 4, 7, 8,
12, 14, 19, 23,
24, 25, 29, 30,
31, 32, 36, 41,
43, 45, 46, 47,
48
2, 4, 6, 8,
22
P
Ground. Connecting all ground pins to a common ground
plane is recommended.
RFO
2
5
-
A resistor to GND sets the operational speed of the chip.
RFO= 5.23K for DS3, RFO=6.81K for E3 and
RFO=4.53K for STS-1.
LF1
26
19
-
Receiver PLL filter capacitor.
Note 1: Pin type: I-input; I3-three level logic input; O-output; P-power supply. Advanced Data sheet pin
assignment and functions are subject to change.
78P7200L
E3/DS3/STS-1
Transceiver
6
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these maximums rating may permanently damage the device.
PARAMETER RATING
Positive supply, V
CC
6V
Storage temperature
-65 to 150
Ambient operating temperature
-40 to +85
C
Output Pin Voltage (LOUT+, LOUT-)
Input Pin Voltage (LIN+, LIN-)
V
CC
-2 to V
CC
+2 V
Input pin voltage, all other pins
V
CC
+0.3 to GND-0.3 V
DC CHARACTERISTICS: Ta = -40
to +85C; positive supply voltage = 5V 0.5V or 3.3V0.3V
PARAMETER PIN
TYPE
CONDITION
MIN
TYP
MAX
UNIT
Supply current I
CC
Transmit and receive all
ones, VCC=5V or 3.3V
70
110
mA
Supply current I
CC
transmitter
disabled,
TXEN=0
35
mA
V
IL
I
0.8
V
V
IH
I
2.0
V
I
IL
, I
IH
I
-10
+10
uA
V
IL3
I3
0.5
V
Z
IM3
I3 Input
Floating
8 10 20 k
V
IH3
I3
V
CC
-0.5
V
I
IL3
, I
IH3
I3
-100
+100
uA
V
OL
O
I
OL
=-0.1mA
0.5
V
V
OH
O
I
OL
=+0.1mA V
CC
-0.5
V
78P7200L
E3/DS3/STS-1
Transceiver
7
E3 receiver (RFO = 6.81k
, E#
E#
E#
E# is set low), receiver is transformer-coupled.
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
Peak Differential Input
Amplitude, LIN+, LIN-
See Note 2
104
1200
mV
pk
Bit Error Ratio in the
presence of an Interfering
Signal at Receive Input
Interfering signal power 20dB below
E3 signal power. Both are PRBS23
(2
23
-1) patterns.
10
-9
RCLK rise/fall time TRCT
2
4
ns
RCLK period, TRCF
29.10 ns
RCLK clock duty cycle
45
55
%
RCLK pulse width TRC
14.55 ns
RPOS/RNEG data setup
time TRDPS
CL=15 pF
7
ns
RPOS/RNEG data hold
time TRDPH
CL=15 pF
7
Note 2: 104 mV
pk
equals 950 mVpk at the source with 1100 feet of cable (13.2dB loss).
78P7200L
E3/DS3/STS-1
Transceiver
8
DS3/STS-1 RECEIVER (RFO = 5.23K
FOR DS3 AND 4.53K
FOR STS-1, E#
E#
E#
E# PIN IS SET HIGH OR
ALLOWED TO FLOAT), INPUT IS TRANSFORMER COUPLED
PARAMETER CONDITION
MIN
TYP
MAX
UNIT
Peak Differential Input
Amplitude, LIN+ and LIN-
(see Note 3)
Signal at DSX is 360-850mVP (see
Note 4)
90 850
mVP
Peak Differential Input
Amplitude, LIN+ and LIN-
DS3 HIGH (see Note 5)
90
1200
mVP
Bit Error Ratio in the presence
of an Interfering Signal (IS) at
LIN+,LIN-
IS is a sinusoidal tone, 22.368 MHz
for DS3 or 25.92MHz for STS-1. Data
is a PRBS15 (2
15
-1) pattern. IS power
is 10dB below data signal power.
10
-9
RCLK rise/fall time TRCT
Cl=25pf
5
ns
RCLK period
TRCF
DS3
STS-1
22.35
19.29
ns
RCLK pulse width
TRC
DS3
STS-1
12.24
9.65
ns
RPOS/RNEG data setup time
TRDPS
CL=15 pF
7
ns
RPOS/RNEG data hold time
TRPDH
CL=15 pF
7
ns
Note 3: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSI-
T102.1993 Figure 5, Loss characteristics of the WE728A or RG 59B cable should be better than Figure C2 of
ANSI-T102.1993.
Note 4: Receiver can handle up to 450 feet of cable loss (5.5dB) from the DSX cross-connect.
Note 5: Case where test signal is fed directly into receiver with fast rise times violates DS3 template and normal
maximum. Interfering signal performance is not guaranteed in the presence of DS3 High at the input..
78P7200L
E3/DS3/STS-1
Transceiver
9
TIMING DIAGRAM: RECEIVE WAVEFORMS (E3/DS3/STS-
1)
RECEIVE LINE
INPUT (REF)
LIN+/LIN-
RCLK
ICKP=LOW or HIGH
RCLK
ICKP=FLOAT
RPOS
RNEG
TRDPS
TRDNS
TRCF
TRCT
TRC
TRDN
TRDNH
TRDPH
TRCT
78P7200L
E3/DS3/STS-1
Transceiver
10
RECEIVER JITTER TOLERANCE
E3 and DS3 jitter tolerance specifications are in ITU-T G.823 and G.824. The test condition can be found in ITU-T
O.171. The E3 specification is the tighter of the two for frequencies greater than 20 kHz. Receive jitter tolerance is
not tested during production test.
PARAMETER CONDITION MIN
NOM
MAX
UNIT
Receiver Jitter Tolerance
12
Hz to 2.78 Hz
10Hz to 600Hz
20 kHz to 800 kHz
18
5
0.15
UI
0.01
0.1
1
10
100
1.E-05
1.E-03
1.E-01
1.E+01 1.E+03 1.E+05 1.E+07
E3
DS3
78P7200L
E3/DS3/STS-1
Transceiver
11
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop filter characteristics are such that the receiver has the following transfer function.
The corner frequency of the PLL is approximately 50 kHz. Receiver jitter transfer function is not tested during
production test.
PARAMETER CONDITION
MIN
NOM
MAX
UNIT
Receiver Jitter transfer function below 59.6 kHz
0.1
dB
Jitter transfer function roll-off
20
dB per decade
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
78P7200L
E3/DS3/STS-1
Transceiver
12
E3 TRANSMITTER (RFO = 6.81K
, E#
E#
E#
E# = LOW)
PARAMETER CONDITION
(SEE TIMING DIAGRAM)
MIN TYP MAX
UNIT
Transmitter amplitude
LOUT+ and LOUT-
900
1000
1100
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse centers
0.95 1.05
Transmitter width mismatch
TTPL/TTHL
Ratio of widths of positive and
negative pulses measured at
pulse half amplitude
0.95 1.05
Transmitter Pulse width TTPL,
TTPN
LOUT+ and LOUT-
14.55
ns
Transmitter clock duty cycle,
TTC/TTCF
40
60
%
Transmitter clock period TTCF
29.10
ns
Transmitter clock pulse width , TTC
14.55
ns
Transmitter clock transition time,
Rising and falling CPTT/CNTT
0.8
3
5
ns
Data setup time TTDRS
2.5
ns
Data hold time TTDHS
2.5
ns
78P7200L
E3/DS3/STS-1
Transceiver
13
DS3/STS-1 TRANSMITTER (
E#
E#
E#
E# = High)
PARAMETER CONDITION MIN
TYP
MAX
UNIT
Transmitter Amplitude
LOUT+ and LOUT-
650
800
850
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
0.9 1.1
Transmitter power
At 22.368 MHz
DS3 only - All ones, 3kHz
bandwidth
-1.8 +5.7
dBm
Transmitter power
At 44.736 MHz
DS3 only - All ones, 3kHz
bandwidth
-21.8 -14.3
dBm
Transmitter clock duty cycle,
TTC/TTCF
40
60
%
Transmitter clock period TTCF
DS3
22.35
ns
Transmitter clock period TTCF
STS-1
19.29
ns
Data setup time TTPDS
2.5
ns
Data hold time TTPDH
2.5
ns
Transmitter clock transition time,
Rising and falling TTCPT,TTCNT
0.8
2
4
ns
78P7200L
E3/DS3/STS-1
Transceiver
14
TIMINGING DIAGRAM: TRANSMITTER WAVEFORMS (E3/DS3/STS-1)
TCLK
ICKP=HIGH or
FLOAT
TCLK
ICKP=LOW
TPOS
TTCF
TTCPT
VP
VN
0.5 VP
0.5 VN
TTC
TTPDS
TTNDS
TTPL
TTNL
TTNDH
TTPDH
TTCNT
78P7200L
E3/DS3/STS-1
Transceiver
15
E3 TRANSMIT TEMPLATE
17 ns
8.65 ns
14.55 ns
12.1 ns
24.5 ns
29.1 ns
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.2
0
0.5
1.0
0.2
78P7200L
E3/DS3/STS-1
Transceiver
16
DS3 TRANSMIT PULSE TEMPLATE
TIME AXIS RANGE (UI)
NORMALIZED AMPLITUDE EQUATION
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.36 < T < 1.4
0.08+0.407 e
-1.84(T-0.36)
LOWER CURVE
-0.85 < T < -0.36
-0.03
-.0.36 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
Nor
m
aliz
ed Am
plitude
78P7200L
E3/DS3/STS-1
Transceiver
17
STS-1 TRANSMIT PULSE TEMPLATE
STS-1 (Transmit template specs)
TIME AXIS RANGE (T)
NORMALIZED AMPLITUDE EQUATION (A)
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.26 < T < 1.4
0.1+0.61 e
-2.4(T-0.26)
LOWER CURVE
-0.85 < T < -0.38
-0.03
-0.38 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
No
rm
aliz
ed
Am
p
lit
u
d
e
78P7200L
E3/DS3/STS-1
Transceiver
18
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, and ANSI T1.102-1993 for all
supported rates. Transmit output jitter is not tested during production test.
Transmitter
Output
Jitter
Detector
Measured Jitter
Amplitude
10Hz
800kHz
20dB/decade
PARAMETER CONDITION MIN
NOM
MAX
UNIT
Transmitter Output Jitter
10 Hz to 800 kHz
0.1
UI
78P7200L
E3/DS3/STS-1
Transceiver
19
E3/DS3/STS-1 EXAMPLE CIRCUIT
Note 6: Pin names in ( ) denote pin names from 78P7200. Pin numbers refer to 28 PLCC package. Default
settings used to simulate 78P7200.
Note 7: Resistors on TCLK, TNEG, TPOS are optional but recommended. Clock pulse shapes at the inputs to the
78P7200L are dependent on board layout and will dictate the need for such added resistors.
Note 8. Adding a series Ferrite Bead on VCC pins may be required for some pc board layout.
EXTERNAL COMPONENTS (COMMON TO E3/DS3/STS-1)
COMPONENT TOLERANCE
VALUE
UNIT
Receiver Termination Resistor
RTR
1%
75
Receiver Transformer Turns Ratio
TR
3%
1:1
---
Transmitter Termination Resistor
RTT
1%
301
Transmitter Transformer Turns Ratio
TT
3%
1:2ct
---
EXTERNAL COMPONENTS (DEPENDANT ON SPEED, NOMINAL VALUE)
COMPONENT TOLERANCE
STS-1
DS3
E3
UNIT
Loop Filter Capacitor
CLF
10%
0.047
0.047
0.047
F
Bias Resistor
RFO
1%
4.53
5.23
6.81
k
Note 9: Advanced Data sheet pin assignment, functions and external component values are subject to change.
78P7200L
E3/DS3/STS-1
Transceiver
20
78P7200L REPLACEMENT FOR EXISTING 78P7200 DESIGNS
COMPONENT VARIATION FOR EXISTING 78P7200 DESIGNS
COMPONENT 78P7200
78P7200L
R1,R2
75
SHORT
(0
)
C2 82p NOT
INSTALLED
L2 6.8u
NOT
INSTALLED
L1 0.47u
NOT
INSTALLED
C1 1000p
NOT
INSTALLED
C3 0.01 NOT
INSTALLED
T1 1:2 1:1
RTR
422
75
INPUT FILTER
CPD 0.22u SHORT (0)
RLF2
100k
NOT INSTALLED
RLF1
6.04k
NOT INSTALLED
PLL FILTER
CLF1 0.22u 0.047u
DS3
301
301
RTT
E3
604
301
DS3
5-15pF NOT
INSTALLED
TRANSMITTER
CTT
E3 3pF
NOT
INSTALLED
POWER SUPPLY
LVCC 4.7uH SHORT (0) or Ferrite
Bead
78P7200L
E3/DS3/STS-1
Transceiver
21
PACKAGE PIN DESIGNATIONS
(Top View)
28-Pin PLCC
(Not drop-in compatible to 78P7200)
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
3
2
1
28 27 26
G
N
D
L
I
N
-
G
N
D
L
I
N
+
L
P
B
K
L
O
S
V
C
C
L
B
O
E
#
R
N
A
Z
T
N
E
G
T
C
L
K
V
C
C
T
X
E
N
RFO
GND
VCC
GND
LOUT+
ICKP
LOUT-
RPOS
RNEG
RCLK
GND
N/ C
N/ C
LF1
CAUTION: Use handling procedures necessary for
a static sensitive component.
78P7200L
E3/DS3/STS-1
Transceiver
22
PACKAGE PIN DESIGNATIONS
(Top View)
48-PIN TQFP
(Not drop-in compatible to 78P7200)
CAUTION: Use handling procedures necessary for
a static sensitive component.
RNEG
1
GND
3
RCLK
2
RFO
4
GND
5
GND
6
VCC
7
GND
8
E#
17
TP
O
S
18
TN
E
G
19
TC
L
K
20
GN
D
21
VC
C
22
VC
C
23
TX
E
N
24
47
GN
D
48
GN
D
46
GN
D
45
GN
D
44
LI
N-
43
GN
D
42
LI
N+
41
GN
D
40
LP
B
K
38
VC
C
37
VC
C
36
GND
LF1
34
35
RPOS
33
GND
32
GND
31
GND
30
GND
29
N/C
LOUT-
13
GND
14
LB
O
15
GN
D
16
GND
9
10
LOUT+
11
ICKP
12
GN
D
28
27
GND
26
GN
D
25
N/C
39
LO
S
VCC
78P7200L
E3/DS3/STS-1
Transceiver
23
MECHANICAL DRAWING
28-Pin PLCC
PIN NO. 1 IDENT.
0.495 (12.573)
0.485 (12.319)
0.495 (12.573)
0.485 (12.319)
0.456 (11.650)
0.450 (11.430)
0.456 (11.650)
0.450 (11.430)
0.075 (1.905)
0.065 (1.651)
0.045 (1.140)
0.020 (0.508)
0.050 (1.270)
0.016 (0.406)
0.020 (0.508)
0.390 (9.906)
0.430 (10.922)
0.165 (4.191)
0.180 (4.572)
78P7200L
E3/DS3/STS-1
Transceiver
24
MECHANICAL DRAWING
48-Pin TQFP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
28-pin PLCC
78P7200L-IH
78P7200L-IH
48-pin
TQFP
78P7200L-IGT
78P7200L-IGT
Advanced Information: Indicates a product is either in prototype testing or undergoing design evaluation prior to full production release.
Specifications are based on design goals or preliminary evaluation and are not guaranteed. Small quantities are usually available and TDK
Semiconductor Corporation should be consulted for current information.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheet is current before placing orders.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877 www.tdksemiconductor.com
2001 TDK Semiconductor Corporation
03/06/01 - rev
.
C
0.2 (0.008) Typ.
INDEX
1
8.7 (0.343)
9.3 (0.366)
1.40 (0.055)
1.60 (0.063)
8.7 (0.343)
9.3 (0.366)
0.50 (0.0197) Typ.
6.8 (0.267)
7.2 (0.283)
0.0 (0)
0.20 (0.008)
0.60 (0.024) Typ.
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