2003 TDK Semiconductor Corporation, Proprietary and Confidential
Rev_1.1
TXD[3:0]
4B/5B Encoder,
Scrambler,
Parallel/Serial
Parallel/Serial,
Manchester Encoder
Manchester Decoder,
Parallel/Serial
Serial/Parallel
Descrambler,
5B/4B Decoder
NRZ/NRZI
MLT3 Encoder
TX CLK GEN
Carrier Sense,
Collision Detect
CLK
Recovery
Clock Reference
100M
10M
25MHz
Pulse Shaper
and Filter
Auto
Negotiation
Adaptive EQ,
Baseline Wander Correct,
MLT3 Decode, NRZI/NRZ
LEDs
LEDL LEDBTX LEDTX LEDCOL
LEDBT LEDFX LEDRX
MDI
10M
100M
CKIN
PS
GND
VCC
MII
Registers
&
Interface
Logic
RXD[3:0]
TX_CLK
RX_CLK
4B/5B Encoder,
Scrambler,
Parallel/Serial
Parallel/Serial,
Manchester Encoder
Manchester Decoder,
Parallel/Serial
Serial/Parallel
Descrambler,
5B/4B Decoder
NRZ/NRZI
MLT3 Encoder
TX CLK GEN
Carrier Sense,
Collision Detect
CLK
Recovery
Clock Reference
100M
10M
25MHz
Pulse Shaper
and Filter
Auto
Negotiation
Adaptive EQ,
Baseline Wander Correct,
MLT3 Decode, NRZI/NRZ
LEDs
MDI
10M
100M
RXIP/N
TXOP/N
PS
GND
VCC
MII
Registers
&
Interface
Logic
78Q2120C
10/100BASE-TX Transceiver
August 2003
DESCRIPTION
The 78Q2120C is a 10BASE-T/100BASE-TX Fast
Ethernet transceiver. It includes integrated MII,
ENDECs, scrambler/descrambler, dual-speed clock
recovery, and full-featured auto-negotiation function.
The transmitter includes an on-chip pulse-shaper and
a low-power line driver. The receiver has an adaptive
equalizer and a baseline restoration circuit required
for accurate clock and data recovery. The transceiver
interfaces to Category-5 unshielded twisted pair (Cat-
5 UTP) cabling for 100BASE-TX/10BASE-T and
Category-3 unshielded twisted pair for 10BASE-T,
and is connected to the line media via 1:1 isolation
transformers. No external filter is required. Interface
to the MAC is accomplished through an IEEE-802.3
compliant Media Independent Interface (MII). The
product is fabricated in an advanced CMOS process
for high performance and low power operation.
FEATURES
10BASE-T/100BASE-TX IEEE-802.3 compliant
TX and RX functions requiring a dual 1:1
isolation transformer interface to the line
Integrated MII, 10BASE-T/100BASE-TX ENDEC,
100BASE-TX scrambler/descrambler, and full-
featured auto-negotiation function
Full duplex operation capable
PCS Bypass supports 5-bit symbol interface
Register-programmable transmit amplitude
Dual speed digital clock recovery
Automatic polarity correction during auto-
negotiation and 10BASE-T signal reception
Power-saving and power-down modes
including transmitter disable
LED indicators: LINK, TX, RX, COL, 100, 10,
FDX
User programmable Interrupt pin
64-Pin TQFP (JEDEC LQFP) package
Single 3.3 V 0.3V Supply
BLOCK DIAGRAM
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FUNCTIONAL DESCRIPTION
GENERAL
Power Management
The 78Q2120C has three power saving modes:
Chip Power-Down
Receive Power Management
Transmit High Impedance Mode
Chip power-down is activated by setting the PWRDN
bit in the MII register (MR0.11) or pulling high the
PWRDN pin. When the chip is in power-down
mode, all on-chip circuitry is shut off, and the device
consumes minimum power. While in power-down
state, the 78Q2120C still responds to management
transactions.
Receive power management (RXCC mode) is
activated by setting the RXCC bit in the MII register
(MR16.0). In this mode of operation, the adaptive
equalizer, the clock recovery phase lock loop (PLL),
and all other receive circuitry will be powered down
when no valid MLT-3 signal is present at the UTP
receive line interface. As soon as a valid signal is
detected, all circuits will automatically be powered
up to resume normal operation. During this mode of
operation, RX_CLK will be inactive when there is no
data being received. Note that the RXCC mode is
not supported during 10BASE-T operation.
Transmit high impedance mode is activated by
setting the TXHIM bit in the MII register (MR16.12).
In this mode of operation, the transmit UTP drivers
are in a high impedance state and TX_CLK is tri-
stated. A weak internal pull-up is enabled on
TX_CLK. The receive circuitry remains fully
operational. The default state of MR16.12 is a logic
low for disabling the transmit high impedance mode.
The transmitter is fully functional when MR16.12 is
cleared.
Analog Biasing and Supply Regulation
The 78Q2120C requires no external component to
generate on-chip bias voltages and currents. High
accuracy is maintained through a closed-loop
trimmed biasing network.
On-chip digital logic runs off an internal voltage
regulator. Hence only a single Vcc supply is
required to power-up the device. The on-chip
regulator is not affected by power-down mode.
Clock Selection
The 78Q2120C will use the on-chip crystal oscillator
as the clock source if the CKIN pin is tied low. In this
mode of operation, a 25MHz crystal should be
connected between the XTLP and XTLN pins.
Alternatively, an external 25MHz clock input can be
connected to the CKIN pin. The chip senses activity
on the CKIN pin, and will automatically configure itself
to use the external clock, if present. In this mode of
operation, a crystal is not required and the XTLP and
XTLN pins should be left floating or connected
together.
Transmit Clock Generation
The transmitter uses an on-chip frequency
synthesizer to generate the transmit clock. In
100BASE-TX operation, the synthesizer multiplies the
reference clock by 5 to obtain the internal 125MHz
serial transmit clock. In 10BASE-T mode, it
generates an internal 20MHz transmit clock by
multiplying the reference 25MHz clock by 4/5. The
synthesizer references either the local 25 MHz crystal
oscillator, or the externally applied clock, depending
on the selected mode of operation.
Receive Signal Qualification
The integrated signal qualifier has separate squelch
and unsquelch thresholds, and includes a built-in timer
to ensure fast and accurate signal detection and line
noise rejection. Upon detection of two or more valid
10BASE-T or 100BASE-TX pulses on the line receive
port, the PASS signal, indicating the presence of valid
receive signal or data, will be asserted. When PASS is
asserted, the signal detect threshold is lowered by
about 60%, and all adaptive circuits are released from
their initial states and allowed to lock onto the incoming
data. In 100BASE-TX operation, PASS will be de-
asserted when no signal is presented for a period of
about 1.2us. In 10BASE-T operation, PASS will be de-
asserted whenever no Manchester data is received. In
either case, the signal detect threshold will return to the
squelched level whenever the PASS indication is de-
asserted. The PASS signal is also used to control the
operation of the clock/data recovery circuit to assure
fast acquisition.
Receive Clock Recovery
In 100BASE-TX mode, the 125MHz receive clock is
extracted using a digital DLL-based loop. When no
receive signal is present, the DLL is directed to lock
onto the 125MHz transmit serial clock. When PASS is
asserted, the DLL will use the received MLT-3 signal
as the clock reference. The recovered clock is used to
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re-time the data signal and for conversion of the data to
NRZ format.
In 10BASE-T mode, the 10MHz receive clock is
recovered digitally from the Manchester data using a
DLL locked to the reference clock. When
Manchester-coded preambles are detected, the DLL
immediately re-aligns the phase of the clock to
synchronize with the incoming data. Hence clock
acquisition is fast and immediate.
100BASE-TX OPERATION
100BASE-TX Transmit
The 78Q2120C contains all of the necessary
circuitry to convert the transmit MII signaling from a
MAC to an IEEE-802.3 compliant data-stream
driving Cat-5 UTP cabling. The internal PCS
interface maps 4 bit nibbles from the MII to 5 bit
code groups as defined in table 24-1 of IEEE-802.3.
These 5 bit code groups are then scrambled and
converted to a serial stream before being sent to the
MLT-3 pulse shaping circuitry and line driver. The
pulse-shaper uses current modulation to produce
the desired output waveform. Controlled rise/fall
time in MLT-3 signal is achieved using an accurately
controlled voltage ramp generator. The line driver
requires an external 1:1 isolation transformer to
interface with the line media. The center-tap of the
primary side of the transformer should be connected
to the Vcc supply.
100BASE-TX Receive
The 78Q2120C receives a 125MBaud MLT-3 signal
through a 1:1 transformer. The signal then goes
through a combination of adaptive offset adjustment
(baseline wander correction) and adaptive
equalization. The effect of these circuits is to sense
the amount of dispersion and attenuation caused by
the cable and transformer, and restore the received
pulses to logic levels. The amount of gain and
equalization applied to the pulses varies with the
detected attenuation and dispersion and, therefore,
with the length of the cable. The 78Q2120C can
compensate for cable loss of up to 10dB at 16 MHz.
This loss is represented as test-chan 5 in Annex A of
the ANSI X3.263:199X specification. The equalized
MLT-3 data signal is bi-directionally sliced and the
resulting NRZI bit-stream is presented to the CDR
where it is re-timed and decoded to NRZ format.
The re-timed serial data is converted to parallel, then
descrambled and aligned into 5 bit code groups.
The receive PCS interface maps these code groups
to 4 bit data for the MII as outlined in Table 24-1 in
Clause 24 of IEEE-802.3.
PCS Bypass Mode (Auto-negotiate must be off)
The PCS Bypass mode is entered by pulling PCSBP
high or by setting register bit MR 16.1. In this mode
the 78Q2120C accepts scrambled 5 bit code words
into the pins TX_ER and TXD[3:0], TX_ER being the
MSB of the data input. The 5 bit code groups are
converted to MLT-3 signal for transmission.
The received MLT-3 signal is converted to 5 bit NRZ
code groups and output from the RX_ER and
RXD[3:0] pins, RX_ER being the MSB of the data
output. The RX_DV and TX_EN pins are unused in
PCS Bypass mode.
10BASE-T OPERATION
10BASE-T Transmit
The 78Q2120C takes 4 bit parallel NRZ data via the
MII interface and passes it through a parallel to
serial converter. The data is then passed through a
Manchester encoder, pre-emphasis pulse-shaper,
media filter, and finally to the twisted-pair line driver.
The pulse-shaper and filter ensures the output
waveforms meet the output voltage template and
spectral content requirements detailed in Clause 14
of IEEE-802.3. Interface to the twisted-pair media is
through two external 50
resistors and a center-
tapped 1:1 transformer. No external filtering is
required. During auto-negotiation and 10BASE-T
idle periods, link pulses are transmitted.
The 78Q2120C employs an onboard timer to
prevent the MAC from capturing a network through
excessively long transmissions. When this timer
expires, the chip enters the jabber state and
transmission is halted. The jabber state is exited
after the MII goes idle for 500
250ms.
10BASE-T Receive
The 78Q2120C receives Manchester-encoded
10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a
smart squelch function. The slicer automatically
adjusts its level after valid data with the appropriate
levels are detected. Data is passed on to the CRU
where the clock is recovered, and the data is re-
timed and decoded. From there, data enters the
serial-to-parallel converter for transmission to the
MAC via the Media Independent Interface. Interface
to the twisted-pair media is through an external
100
shunt resistor and a 1:1 transformer. Polarity
information is detected and corrected within internal
circuitry.
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Polarity Correction
The 78Q2120C is capable of either automatic or
manual polarity reversal for 10BASE-T and auto-
negotiation functions. Register bits MR16.5 and
MR16.4 control this feature. The default is
automatic mode where MR16.5 is low and MR16.4
indicates if the detection circuitry has inverted the
input signal. To enter manual mode, MR16.5 should
be set high and MR16.4 will then control the signal
polarity.
SQE TEST
The 78Q2120C supports the Signal Quality Error
(SQE) function detailed in IEEE-802.3. At an
interval of 1
s after each negative transition of the
TXEN pin in 10BASE-T mode, the COL pin will go
high for a period of 1
s. This function can be
disabled through register bit MR16.11.
Natural Loopback
When enabled, whenever the 78Q2120C is
transmitting and not receiving on the twisted pair
media (10BASE-T Half Duplex mode), data on the
TXD[3:0] pins is looped back onto the RXD[3:0] pins.
During a collision, data from the RXI pins is routed to
the RXD[3:0] pins. The natural loopback function is
enabled through register bit MR16.10.
Repeater Mode
When the RPTR pin is high or register bit MR16.15
is set, the 78Q2120C is placed in repeater mode. In
this mode, full duplex operation is prohibited, CRS
responds only to receive activity and, in 10BASE-T
mode, the SQE test function is disabled.
AUTO-NEGOTIATION
The 78Q2120C supports the auto-negotiation
functions of Clause 28 of IEEE-802.3. This function
can be enabled via a pin selection or register
settings. If the ANEGA pin is tied high, the auto-
negotiation function defaults to ON and bit MR0.12
(ANEGEN) is high after reset. Software can disable
the auto-negotiation function by writing to bit
MR0.12. If the ANEGA pin is tied low, the function
defaults to OFF and bit MR0.12 is set low after reset
and cannot be written to.
The contents of register MR4 are sent to the
78Q2120C's link partner during auto-negotiation,
coded in fast link pulses. Bits MR4.8:5 reflect the
state of the TECH[2:0] pins after reset. If TECH[2:0]
= `111', then all 4 bits are high. If TECH[2:0] = `001',
then only bit 5 is high. After reset, software can
change any of these bits from a `1' to a `0'; but not
from a `0' to a `1'. Therefore, a technology permitted
by the setting of the TECH pins can be disabled, but
cannot be enabled through register selection.
With auto-negotiation enabled, the 78Q2120C will
start sending fast link pulses at power on, loss of link
or a command to restart. At the same time, it will
look for either 10BASE-T idle, 100BASE-TX idle, or
fast link pulses from its link partner. If either idle
pattern is detected, the 78Q2120C configures itself
in half-duplex mode at the appropriate speed. If it
detects fast link pulses, it decodes and analyzes the
link code transmitted by the link partner. When
three identical link code words are received (ignoring
the acknowledge bit) the link code word is stored in
register MR5. Upon receiving three more identical
link code words, with the acknowledge bit set, the
78Q2120C configures itself to the highest priority
technology common to the two link partners. The
technology priorities are, in descending order:
100BASE-TX, Full Duplex
100BASE-TX, Half Duplex
10BASE-T, Full Duplex
10BASE-T, Half Duplex
Once auto-negotiation is complete, register bits
MR18.11:10 will reflect the actual speed and duplex
that was chosen.
If auto-negotiation fails to establish a link for any
reason, register bit MR18.12 will reflect this and auto
negotiation will restart from the beginning. Writing a
`1' to bit MR0.9(RANEG) will also cause auto-
negotiation to restart.
MEDIA INDEPENDENT INTERFACE
MII Transmit and Receive Operation
The MII interface on the 78Q2120C provides
independent transmit and receive paths for both
10Mb/s and 100Mb/s data rates as described in
Clause 22 of the IEEE-802.3 standard.
The transmit clock, TX_CLK, provides the timing
reference for the transfer of TX_EN, TXD[3:0], and
TX_ER signals from the MAC to the 78Q2120C.
TXD[3:0] is captured on the rising edge of TX_CLK
when TX_EN is asserted. TX_ER is also captured
on the rising edge of TX_CLK and is asserted by the
MAC to request that an error code group be
transmitted. The assertion of TX_ER has no affect
when the 78Q2120C is operating in 10BASE-T
mode.
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, RXD[3:0], and RX_ER
signals from the 78Q2120C to the MAC. RX_DV
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transitions synchronously with respect to RX_CLK
and is asserted when the 78Q2120C is presenting
valid data on RXD[3:0]. RX_ER is asserted when a
code group violation has been detected in the
current receive packet and is also synchronous to
RX_CLK.
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.5 of IEEE-802.3. A 16-
bit shift register receives serial data applied to the
MDIO pin at the rising-edge of the MDC clock signal.
Once the preamble is received, the station
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. For a
read operation, the MDIO port becomes enabled as
an output and the register data is loaded into a shift
register for transmission. The 78Q2120C can work
with a one bit preamble rather than the 32 bits
proscribed by IEEE-802.3. This allows for faster
programming of the registers. If a register does not
exist at an address indicated by the REGAD field or
if the PHYAD field does not match the 78Q2120C
PHYAD indicated by the PHYAD pins, a read of the
MDIO port will return all ones. For a write operation,
the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been
received.
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
data transaction. All PHYs sharing the same
Management Interface must respond to this
broadcast request. The 78Q2120C will respond to
the broadcast data transaction.
ADDITIONAL FEATURES
LED Indicators
There are seven LED pins that can be used to
indicate various states of operation of the
78Q2120C. There is an LED pin that indicates the
link is up (
LEDL), others that indicates the
78Q2120C is either transmitting (
LEDTX) or
receiving (
LEDRX), one that signals a collision event
(
LEDCOL), two more that reflect the data rate
(
LEDBTX and LEDBT), and one that reflects full
duplex mode of operation (
LEDFDX).
Interrupt Pin
The 78Q2120C has an Interrupt pin (INTR) that is
asserted whenever any of the eight interrupt bits of
MR17.7:0 are set. These interrupt bits can be
disabled via MR17.15:8 Interrupt Enable bits. The
Interrupt Level bit, MR16.14, controls the active level
of the INTR pin. When the INTR pin is not asserted,
the pin is held in a high impedance state.
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