78Q2132
1/10BASE-T
HomePNA/Ethernet Transceiver
Advanced Information
August 2000
DESCRIPTION
The 78Q2132 is a 1/10 Ethernet transceiver. This
dual speed transceiver interfaces to a 1Mbps Home
LAN and a 10BASE-T network. The Home LAN
interface is fully Home Phoneline Networking Alliance
(HomePNA) compliant extending Ethernet over
POTS. The HomePNA interface includes the pulse
encoder and decoder plus transmit and receive line
interface filters. Only a telco transformer and external
protection devices are required to complete the
interface. The 78Q2132 also integrates MII and
General Purpose Serial Interface (GPSI) MAC
interfaces. The 10BASE-T Ethernet channel includes
Manchester ENDEC and transmitter with an on-chip
pulse-shaper and a low-power line driver. The
10BASE-T transceiver interfaces to Category-3
unshielded twisted pair (Cat-3 UTP) cabling. The
HomePNA port is connected to the line via a
HomePNA compatible 1:1 transformer having a
series capacitor in the line side and the Ethernet port
is connected to the line via 1:1 (Rx) and 1.414:1 (Tx)
isolation transformers. No external filtering is
required. Communication to the MAC is accomplished
through an IEEE-802.3 compliant media independent
interface (MII) or GPSI. The product is designed for
high performance and low power operation, and can
operate from a single 3.3 V or 5 V supply.
FEATURES
1M8 Home LAN interface over POTS
HomePNA 1.1 compliant
Integrated HomePNA interface and line filters
Simultaneous Spectral Compatibility with
Voice, Fax, ISDN, xDSL, Cable Modem with
HomePNA
10BASE-T IEEE-802.3 compliant TX and RX
functions requiring only a dual isolation
transformer interface to the line
Integrated MII, GPSI and 10BASE-T ENDEC
Full duplex operation capable in 10BASE-T
Automatic polarity correction for 10BASE-T
signal reception
Power-saving and power-down modes
including transmitter disable
Operates with a single 3.3V or 5V supply
LINK, TX, RX, COL, 10, 1, FDX/SPD, PWR
LED indicators
User programmable Interrupt pin
General Purpose I/O Interface
80-Lead or 64-Lead TQFP package
TYPICAL APPLICATION DIAGRAM
Target Specification
78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
2
FUNCTIONAL DESCRIPTION
GENERAL
Supply Voltage
The 78Q2132 can operate from either a single 3.3V
(
0.3V) or 5.0V (
0.5V) power supply. The chip
automatically adapts to the supply voltage used. No
pin configuration is required.
Power Management
Chip power-down is activated by setting the PWRDN
bit in the MII register (MR0.11) or pulling high the
PWRDN pin. When the chip is in power-down
mode, all on-chip circuitry is shut off, and the device
consumes minimum power. While in power-down
state, the 78Q2132 still responds to the
management transactions.
Analog Biasing
The 78Q2132 uses the onchip bandgap and an
external resistor to generate accurate bias voltages
and currents for the circuitry.
Clock Input
The 78Q2132 can use the on-chip crystal oscillator. In
this mode a 25MHz crystal is connected between the
XTAL_IN and XTAL_OUT pins. Alternatively, an
externally generated 25MHz clock can be connected
to the XTAL_IN pin. In conjunction with the oscillator
the device uses a PLLOSC to generate 60MHz which
is divided down by 3 to create 20MHz. It is further
divided for use by various functions on the chip. The
HomePNA section uses the time unit, TIC defined as
60MHz/7 (approx. 116.6ns).
HOMEPNA OPERATION
HomePNA Transmit
The 78Q2132 contains all of the necessary pulse
waveform circuitry to convert the transmit signaling
from a MAC to a HomePNA compliant data-stream.
The conversion is from either a 4bit parallel data
word via the MII interface or the serial data-stream
from GPSI interface to a serial data stream to a
RLL25 encoded set of 3 to 6bits. The value created,
between 0 and 24, is used to modulate the time, in
TIC increments, between pulse bursts. The pulse
bursts are filtered to bandlimit the signal passed to
the line driver, and to the line for transmission. The
integrated envelop-shaper reduces out-of-band
energy to reduce interference. The line driver
requires an external 1:1 isolation transformer to
interface with the line media. Only an external
transient protector and a couple of EMI suppression
inductors are required with the transformer. Note
the transformer requires a coupling capacitor on the
line side.
The 78Q2132 conforms to the required envelope for
transmission bursts on the line. See Figure 6 for the
detail of a single pulse burst signal.
The output is fed to a bandpass filter to reduce out-of-
band components. When not transmitting the transmit
circuitry is put into a mode that rejects common-mode
signals appearing at the receiver input.
HomePNA Receive
The 78Q2132 receives the encoded digital signal
through the same 1:1 transformer used for
transmission. The signal is internally filtered and
compared to an adjusted noise threshold prior to
being decoded. From the resulting signal and
internal time reference a value is assigned to the
time interval. The value is RLL25 decoded and the
bit-stream is presented to the serial to parallel
converter. The parallel data from the converter is
then aligned and mapped as a 4 bit data for the MII
as outlined in Table 24-1 in Clause 24 of IEEE-802.3
or sent to the serial GSPI interface.
The receive channel consists of a prefilter,
AGC/main filter, FWR, LPF and comparator with
adjustable level. Following the prefilter is a 2-level
AGC that compresses the dynamic range
requirements of the signal prior to going through the
main HomePNA receive filter.
Natural Loopback
When the 78Q2132 is transmitting on the twisted
pair media, data on the TXD pins is looped back
onto the RXD pins. The natural loopback function
can be disabled through register bit MR16.10.
REFERENCE PACKET FRAMING AND
SEQUENCE
The frame passed between the MAC and 1M8 PHY
on TX-DATA and RX-DATA conforms to the 802.3
Ethernet MAC frame. When a pulse begins
transmission, the previous Symbol interval ends and
a new one immediately begins.
The Run Length Limit (RLL25) code was developed
for the 1M8 PHY. It produces both the highest bit
rate for a given value of Inter Symbol Blanking
Interval (ISBI) and Time Interval Clock (TIC) size. In
a manner similar to run length limited disk coding,
RLL25 encodes data bits in groups of varying sizes,
78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
3
specifically, 3,4,5 and 6 bits. Pulse positions are
assigned to the encoded bit groups in a manner that
causes more data bits to be encoded in positions
that are farther apart. This keeps both the average
and minimum bit rates higher.
HomePNA 1.1 Compatibility
MR19.11 will reflect the version of HomePNA to be
utilized to set the Link Status bit MR1.2. When
MR19.11 is a logic zero, the device will behave as a
HomePNA v1.0 compliant PHY. This will result in
the Link Status bit MR1.2 always being logic one. If
MR19.11 is set to logic one, the device will behave
as a HomePNA 1.1 compliant PHY.
To enable link integrity checking as specified by
HomePNA v1.1, the PHY continually checks for
packet reception. Upon a lapse of packets greater
than 4seconds, the link status bit, MR1.2, is cleared.
Also, for HomePNA v1.1 compatibility, the PHY can
be commanded to place a RUNT or MINIMUM
packet out at any time. These packets, along with
normal packets, indicate to other transceivers that
the link is up when sent at least every 2seconds.
10BASE-T OPERATION
10BASE-T Transmit
The 78Q2132 takes 4 bit parallel NRZ data via the
MII interface and passes it through a parallel to
serial converter. The data is then passed through a
Manchester encoder and then on to the twisted pair
pulse shaping circuitry and the twisted pair drive
circuitry. An advanced pulse shaper employs a Gm-
C filter to pre-distort the output waveform to meet the
output voltage template and spectral content
requirements detailed in Clause 14 of IEEE-802.3.
Interface to the twisted pair media is through a
center-tapped 1.414:1 transformer with 100 ohm
load resistors; no external filtering is required.
During 10BASE-T idle periods, normal link pulses
(NLP) are transmitted. During auto-negotiation of
half or full duplex, fast link pulses (FLP) are
transmitted. When neither data nor link pulses are
being transmitted, the bias current to the transmitter
is cut to 1% of normal. This reduces the power
consumption during idle periods.
The 78Q2132 employs an onboard timer to prevent
the MAC from capturing a network through
excessively long transmissions. When this timer is
exceeded the chip enters the Jabber State, and
transmission is disabled. The jabber state is exited
after the MII goes idle for 500ms
250ms.
10BASE-T Receive
The 78Q2132 receives Manchester encoded
10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a
smart squelch function. The slicer automatically
adjusts its level after valid data with the appropriate
levels are detected. Data is passed on to the
10BASE-T PLL where the clock is recovered, data is
re-timed and passed through a Manchester decoder.
From here data enters the serial to parallel converter
for transmission to the MAC via the media
independent interface. Interface to the twisted pair
media is through an external 100 ohm resistor and a
1:1 center-tapped transformer; no external filtering is
required. Polarity information is detected and
corrected in the internal circuitry.
Receive Signal
The integrated signal qualifier has separate squelch and
un-squelch thresholds, and includes a built-in timer to
ensure fast and accurate signal detection and receive
noise rejection. Upon detection of two or more valid
10BASE-T pulses on the line receive port, the pass
indication, indicating the presence of valid receive signals
or data, will be asserted. When pass is asserted, the
signal detect threshold is lowered by about 60%, and all
adaptive circuits are released from their quiescent
operating conditions, allowing them to lock onto the
incoming data. In 10BASE-T operation, pass will be de-
asserted whenever no Manchester data is received. In
either case, the signal detect threshold will return to the
squelched level whenever the pass indication is de-
asserted. The pass signal is used internally to control the
operation of the receive clock recovery.
Receive Clock Recovery
In 10BASE-T mode, the 10MHz clock is recovered
using a PLL. For fast acquisition, the receive PLL is
locked onto the transmit reference clock during idle
receive periods. When Manchester-coded preambles
are detected, the PLL adjusts its phase and re-
synchronizes with the incoming Manchester data.
Polarity Correction
The 78Q2132 is capable of either automatic or
manual polarity reversal for 10BASE-T and auto-
negotiation. Register bits MR16.5 and MR16.4
control these features. The default is automatic
mode where MR16.5 is low and MR16.4 indicates if
the detection circuitry has inverted the input signal.
To enter manual mode, MR16.5 is set high and
MR16.4 will then control the signal polarity.
78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
4
SQE Test
The 78Q2132 supports the signal quality error (SQE)
function detailed in IEEE-802.3. At an interval of 1
s after each negative transition of the TXEN pin in
10BASE-T mode, the COL pin will go high for a
period of 1
s. This function can be disabled through
register bit MR16.11.
Natural Loopback
When the 78Q2132 is transmitting and not receiving
on the twisted pair media, data on the TXD pins is
looped back onto the RXD pins. During a collision,
signal from the analog receive pins is decoded and
sent to the digital RXD pins, as normal. The natural
loopback function can be enabled through register
bit MR16.10.
Auto-Negotiation
The 78Q2132 supports the auto-negotiation function
of Clause 28 of IEEE-802.3 for 10BASE-T half and
full duplex technologies. This function can be
enabled via a pin strap to the device or through
registers. If the ANEGA pin is tied high, the auto-
negotiation function defaults to on and bit MR0.12,
ANEGEN, is high after reset. Software can disable
the auto-negotiation function by writing to bit
MR0.12. If the ANEGA pin is tied low the function
defaults to off and bit MR0.12 is set low after reset
and cannot be written.
The contents of MII Register MR4 are sent to the link
partner during auto-negotiation encoded in FLPs.
Technology ability bits MR4.9: 7 are not supported
and are permanently tied low. Bits MR4.6:5 reflect
the state of the TECH[2:0] pins.
After reset, software can disable the bits but they
cannot be enabled unless it's corresponding
technology is permitted by the TECH pins.
With auto-negotiation enabled the 78Q2132 will start
sending FLPs at power-up, loss of link or a
command to restart, if the HomePNA mode is not
selected. At the same time it will look for either
10BASE-T idle or FLPs from its link partner. If
10BASE-T idle pattern is detected, the 78Q2132
realizes that its link partner is not capable of auto-
negotiation, falls into parallel detect mode and
configures itself to half-duplex mode. If FLPs are
detected, it decodes and analyzes the link code
word (LCW) transmitted by the link partner. When
three identical LCWs are received (ignoring the
acknowledge bit) the LCW is stored in register 5.
Upon receiving three more identical LCWs, with the
acknowledge bit set, the 78Q2132 configures itself
to either full duplex or half duplex, which ever is
common to the two link partners with Full Duplex
taking priority.
Once auto-negotiation is complete, register bit
MR18.10 will reflect the duplex mode that was
chosen. If HomePNA mode is selected, auto-
negotiation is disabled and this bit has no meaning.
If auto-negotiation fails to establish a link for any
reason, register bit MR18.12 will reflect this and
auto-negotiation will restart from the beginning.
Writing a one to bit MR0.9, RANEG, will also cause
auto-negotiation to restart.
MEDIA INDEPENDENT INTERFACE
MII Transmit and Receive Operation
The MII interface on the 78Q2132 provides
independent transmit and receive paths for the
1Mb/s HomePNA interface and the 10Mb/s 10BASE-
T data rate as described in Clause 22 of the IEEE-
802.3 standard.
The transmit clock, TX_CLK, provides the timing
reference for the transfer of TX_EN, and TXD[3:0],
signals from the MAC to the 78Q2132. TXD[3:0] is
captured on the rising edge of TX_CLK when
TX_EN is asserted.
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, and RXD[3:0], signals
from the 78Q2132 to the MAC. RX_DV transitions
synchronously with respect to RX_CLK and is
asserted when the 78Q2132 is presenting valid data
on RXD[3:0].
General Purpose Serial Interface
The seven signals which comprise the GPSI are
TX_CLK, TX_EN, TX_DATA, RX_CLK, RX_DATA,
CRS, and CLSN. Of these, only TX_EN and
TX_DATA are inputs to the 2132; the other five are
outputs from the 2132.
The transmit clock, TX_CLK, provides the timing
reference for the transfer of TX_EN and TX_DATA
signals from the MAC to the 2132. TX_DATA is
captured on the rising edge of TX_CLK when
TX_EN is asserted.
The receive clock, RX_CLK, provides the timing
reference to transfer the RX_DATA signal from the
2132 to the MAC.
RX_DATA transitions
synchronously on the rising edge of RX_CLK.
78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
5
Carrier Sense, CRS, is asserted high whenever a
non-idle condition exists on either the receiver or the
transmitter. Typically, GPSI MACs will ignore CRS
during transmit modes.
The Collision signal, CLSN, indicates a collision has
been detected by the 2132 on the wiring network.
MII/GPSI Selection
The MII on the 78Q2132 is internally connected to
the transmit and receive paths for either the 1M8
HomePNA or the 10BASE-T interface as described
in Clause 22 of the IEEE 802.3 standard. The
MII_EN pin selects the choice of interface or MII
Enable bit MR16.1. If the HomePNA port is enabled
the MII_EN pin or MII_Enable bit can select either
the MII or GPSI Interface. If the device is in
10BASE-T operation both the MII_EN pin and MII
Enable bit will have no effect on the selection
between MII and GPSI.
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.4 of IEEE-802.3. A 16-bit
shift register receives serial data applied to the
MDIO pin at the rising edge of the MDC clock signal.
Once the preamble is received, the station
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. For a
read operation, the MDIO port becomes enabled as
an output and the register data is loaded into a shift
register for transmission. The 78Q2132 can work
with a one-bit preamble rather than the 32 bits
prescribed by IEEE-802.3. This allows for faster
programming of the registers. If a register does not
exist at an address indicated by the REGAD field or
if the PHYAD field does not match the 78Q2132
PHYAD indicated by the PHYAD pins, a read of the
MDIO port will return all ones. For a write operation,
the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been
received. Writes to registers not supported by the
78Q2132 are ignored.
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
data transaction. All PHYs sharing the same
Management Interface must respond to this
broadcast request. The 78Q2132 responds to the
broadcast data transaction.
ADDITIONAL FEATURES
LED Indicators
There are eight LED pins that can be used to
indicate various states of operation of the 2132.
There are LED pins that indicate when the 2132 is
either transmitting LEDTX or receiving LEDRX, one
that signals a collision event LEDCOL, two more that
reflect the data rate LED1 and LED10. LFD_SPD
reflects full duplex mode of operation when in 802.3
mode and transmit speed when in HomePNA mode.
LEDL indicates the link is up in either mode. The
LEDPWR pin indicates the power level of the
HomePNA port.
General Purpose I/O Interface
The 78Q2132 has a two pin, bi-directional, general
purpose interface that can be used for external
control or to monitor external signals. The direction
of these pins and the data that is either driven or
read from these pins is configured via bits MR16.9:6
as detailed in the Vendor Specific Register
description in MR16.
Interrupt Pin
The 78Q2132 has an Interrupt pin (INTR) that is
asserted whenever any of the Twenty Four interrupt
bits of MR17.7:0 for 10BASE-T and P1R3 15:0 for
HomePNA are set. These interrupt bits can be
disabled via MR17.15:8 and MR19.12 Interrupt
Enable bits. The Interrupt Level bit, MR16.14,
controls the active level of the INTR pin. When the
INTR pin is not asserted, the pin is held in a high
impedance state.
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