Document Outline
- Return to Contents
- List of Figures
- 1. Push-button Reset
- 2. Watchdog Timer
- 3. Push-button Reset.
- 4. Strobe Input
- 5. Power-Down Slew Rate
- 6. Power-Up Slew Rate
- 7. VCC Detect Reset Output Delay (Power-Down)
- 8. VCC Detect Reset Output Delay (Power-Up)
- Features
- Applications
- Ordering Information
- Functional Block Diagram
- General Description
- Absolute Maximum Ratings*
- DC Electrical Characteristics
- Capacitance (Note 4)
- AC Electrical Characteristics
- AC Electrical Characteristics (Cont.)
- Pin Configurations
- Pin Description
- Detailed Description
- Power Monitor
- Push-button Reset Input
- Watchdog Timer
- Supply Monitor Noise Sensitivity
5-19
TELCOM SEMICONDUCTOR, INC.
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PRELIMINARY INFORMATION
TC1232
FEATURES
s
Precision Voltage
Monitor ....................... Adjustable +4.5V or +4.75V
s
Reset Pulse Width ............................. 250msec Min
s
No External Components
s
Adjustable Watchdog
Timer ........................ 150msec, 600msec or 1.2sec
s
Debounced Manual Reset Input for External
Override
MICROPROCESSOR MONITOR
APPLICATIONS
s
Computers
s
Controllers
s
Intelligent Instruments
s
Automotive Systems
s
Critical
P Power Monitoring
FUNCTIONAL BLOCK DIAGRAM
V
CC
TC1232
+
5%/10%
TOLERANCE
SELECT
TOL
DEBOUNCE
WATCHDOG
TIMEBASE
SELECT
PB RST
TD
GND
REF
WATCHDOG
TIMER
RESET
GENERATOR
RST
RST
ST
+
ORDERING INFORMATION
Part No.
Package
Temp. Range
TC1232COA
8-Pin SOIC
0
C to +70
C
TC1232COE
16-Pin SOIC (Wide)
0
C to +70
C
TC1232CPA
8-Pin PDIP
0
C to +70
C
TC1232EOA
8-Pin SOIC
40
C to +85
C
TC1232EOE
16-Pin SOIC (Wide)
40
C to +85
C
TC1232EPA
8-Pin PDIP
40
C to +85
C
TC1232-4 11/6/96
GENERAL DESCRIPTION
The TC1232 is a fully-integrated processor supervisor.
It provides three important functions to safeguard processor
sanity: precision power on/off reset control, watchdog timer
and external reset override.
On power-up, the TC1232 holds the processor in the
reset state for a minimum of 250msec after V
CC
is within
tolerance to ensure a stable system start-up.
Microprocessor sanity is monitored by the on-board
watchdog circuit. The microprocessor must provide a peri-
odic low-going signal on the ST input. Should the processor
fail to supply this signal within the selected time-out period
(150msec, 600msec or 1200msec), an out-of-control pro-
cessor is indicated and the TC1232 issues a processor reset
as a result.
The outputs of the TC1232 are immediately driven
active when the PB input is brought low by an external push-
button switch or other electronic signal. When connected to
a push-button switch, the TC1232 provides contact
debounce.
The TC1232 is packaged in a space-saving 8-pin plastic
DIP or SOIC package and requires no external components.
5-20
TELCOM SEMICONDUCTOR, INC.
TC1232
MICROPROCESSOR MONITOR
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin (With Respect to GND) 0.3V to +5.8V
Operating Temperature Range:
TC1232C .......................................... 0
C to +70
C
TC1232E ..................................... 40
C to + 85
C
Storage Temperature Range ................ 65
C to +150
C
Lead Temperature (Soldering, 10 sec) ................. +300
C
*Stresses beyond those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS:
T
A
= T
MIN
to T
MAX;
V
CC
=
+4.5V
to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
IH
ST and PB RST
2.0
--
V
CC
+0.3
V
Input High Level
Note 1
V
IL
ST and PB RST
0.3
--
+0.8
V
Input Low Level
I
L
Input Leakage ST, TOL
1.0
--
+1.0
A
I
OH
Output Current RST
V
OH
= 2.4V
1.0
12
--
mA
I
OL
Current RST, RST
V
OL
= 0.4V
2.0
10
--
mA
I
CC
Operating Current
Note 2
--
50
200
A
V
CCTP
V
CC
5% Trip Point (Note 3)
TOL = GND
4.50
4.62
4.74
V
V
CCTP
V
CC
10% Trip Point (Note 3)
TOL = V
CC
4.25
4.37
4.49
V
AC ELECTRICAL CHARACTERISTICS:
T
A
= T
MIN
to T
MAX;
V
CC
=
+5V
to +10%, unless otherwise specified.
Symbol
Parameters
Test Conditions
Min
Typ
Max
Units
t
PB
PB RST (Note 5)
Figure 3
20
--
--
msec
t
PBD
PB RST Delay
Figure 3
1
4
20
msec
t
RST
Reset Active Time
250
610
1000
msec
t
ST
ST Pulse Width
Figure 4
75
--
--
nsec
t
TD
ST Time-out Period
Figure 4
TD Pin = 0V
62.5
150
250
msec
TD Pin = Open
250
600
1000
msec
TD Pin = V
CC
500
1200
2000
msec
t
F
V
CC
Fall Time (Note 4)
Figure 5
10
--
--
sec
CAPACITANCE (Note 4):
T
A
= +25
C
Symbol
Parameters
Test Conditions
Min
Typ
Max
Units
C
IN
Input Capacitance ST, TOL
--
--
5
pF
C
OUT
Output Capacitance RST, RST
--
--
7
pF
5-21
TELCOM SEMICONDUCTOR, INC.
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AC ELECTRICAL CHARACTERISTICS: (Cont.
) T
A
= T
MIN
to T
MAX
; V
CC
=
+5V
to +10%, unless otherwise
specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
t
R
V
CC
Rise Time (Note 4)
Figure 6
0
--
--
sec
t
RPD
V
CC
Detect to RST High
Figure 7, V
CC
Falling
--
--
100
nsec
and RST Low
t
RPU
V
CC
Detect to RST High
Figure 8, V
CC
Rising
250
610
1000
msec
and RST Open (Note 6)
PIN DESCRIPTION
Pin No.
Pin No.
Pin No.
(8-Pin PDIP) (8-Pin SOIC) (16-Pin SOIC) Symbol Description
1
1
2
PB RST Push-button Reset Input. A debounced active-low input that ignores
pulses less than 1msec in duration and is guaranteed to recognize inputs
of 20msec or greater.
2
2
4
TD
Time Delay Set. The watchdog time-out select input (t
TD
= 150msec for
TD = 0V, t
TD
= 600msec for TD = open, t
TD
= 1.2sec for TD = V
CC
).
3
3
6
TOL
Tolerance Input. Connect to GND for 5% tolerance or to V
CC
for 10%
tolerance.
4
4
8
GND
Ground.
5
5
9
RST
Reset Output (Active High) - goes active:
1. If V
CC
falls below the selected reset voltage threshold
2. If PB RST is forced low
3. If ST is not strobed within the minimum time-out period
4. During power-up
6
6
11
RST
Reset Output (Active Low, Open Drain) - see RST.
7
7
13
ST
Strobe Input. Input for watchdog timer.
8
8
15
V
CC
The +5V Power-Supply Input.
1, 3, 5, 7, 10,
NC
No Internal Connection.
12, 14, 16
NOTES: 1. PB RST is internally pulled up to V
CC
with an internal impedance of typically 40k
.
2. Measured with outputs open.
3. All voltages referenced to GND.
4. Guaranteed by design.
5. PB RST must be held low for a minimum of 20msec to guarantee a reset.
6. t
R
= 5
sec.
1
8
2
7
3
6
4
5
TC1232CPA
TC1232EPA
RST
RST
GND
TOL
TD
PB RST
RST
ST
V
CC
RST
ST
1
8
2
7
3
6
4
5
RST
GND
TOL
TD
PB RST
RST
ST
V
CC
PB RST
TC1232COA
TC1232EOA
V
1
2
3
4
5
6
7
8
16
13
12
11
10
9
NC
TD
NC
NC
15
14
TOL
GND
NC
NC
NC
TC1232COE
TC1232EOE
NC
CC
NC
16-Pin SOIC Wide
8-Pin PDIP
8-Pin SOIC
PIN CONFIGURATIONS
TC1232
MICROPROCESSOR MONITOR
5-22
TELCOM SEMICONDUCTOR, INC.
V
CC
TOL GND
RST
ST
RESET
+5V
TC1232
TD
0.1
F
10K
I/O
MICROPROCESSOR
3 -TERMINAL
REGULATOR
+5V
V
CC
TOL
PB RST
GND
RST
ST
I/O
MICROPROCESSOR
RESET
+5V
TC1232
TD
Figure 2. Watchdog Timer
Figure 1. Push-button Reset
mode and set it low while in the background or interrupt
mode. If both modes do not execute correctly, the watchdog
timer issues reset pulses.
Supply Monitor Noise Sensitivity
The TC1232 is optimized for fast response to negative-
going changes in V
DD
. Systems with an inordinate amount
of electrical noise on V
DD
(such as systems using relays),
may require a 0.01
F or 0.1
F bypass capacitor to reduce
detection sensitivity. This capacitor should be installed as
close to the TC1232 as possible to keep the capacitor lead
length short.
DETAILED DESCRIPTION
Power Monitor
The TC1232 detects out-of-tolerance power supply
conditions and warns a processor-based system of an
impending power failure. When V
CC
is detected as below the
preset level defined by TOL, the V
CC
comparator outputs the
signals RST and RST. If TOL is connected to ground, the
RST and RST signals become active as V
CC
falls below 4.75
volts. If TOL is connected to V
CC
, the RST and RST become
active as V
CC
falls below 4.5 volts. Because the processing
is stopped at the last possible moment of valid V
CC,
the RST
and RST are excellent control signals for a
P. The reset
outputs will remain in their active states until V
CC
has been
continuously in-tolerance for a minimum of 250msec allow-
ing the power supply and
P to stabilize before RST is
released.
Push-button Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once
PB RST has been low for a time t
PBD,
the push-button delay
time, the reset outputs go active. The reset outputs remain
in their active states for a minimum of 250msec after PB RST
rises above V
IH
(Figure
3).
A mechanical push-button or active logic signal can
drive the PB RST input. The debounced input ignores input
pulses less than 1msec and is guaranteed to recognize
pulses of 20msec or greater. No external pull-up resistor is
required
because the PB RST input has an internal pull-up
to
V
CC
of
approximately 100
A.
Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is deter-
mined by the TD inputs to be 150msec with TD connected
to ground, 600msec with TD floating, or 1200msec with TD
connected to V
CC,
typical. The watchdog timer starts timing
out from the set time period as soon as RST and RST are
inactive. If a high-to-low transition occurs on the ST input pin
prior to time-out, the watchdog timer is reset and begins to
time-out again. If the watchdog timer is allowed to time-out,
then the RST and RST signals are driven to the active state
for 250msec minimum (Figure 2).
The software routine that strobes ST is critical. The code
must be in a section of software that is executed frequently
enough so the time between toggles is less than the watch-
dog time-out period. One common technique controls the
P
I/O line from two sections of the program. The software
might set the I/O line high while operating in the foreground
TC1232
MICROPROCESSOR MONITOR
5-23
TELCOM SEMICONDUCTOR, INC.
7
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TC1232
MICROPROCESSOR MONITOR
RST
V
IL
t
PB
RST
t
PBD
V
IH
t
RST
PB RST
Figure 3. Push-button Reset. The debounced PB RST input
ignores input pulses less than 1msec and is guaranteed
to recognize pulses of 20msec or greater
Figure 4. Strobe Input
Figure 5. Power-Down Slew Rate
Figure 6. Power-Up Slew Rate
+4.75V
t
F
V
CC
+4.25V
t
R
V
CC
+4.25V
+4.75V
t
ST
ST
t
TD
NOTE:
t
TD IS THE MAXIMUM ELAPSED TIME BETWEEN ST HIGH-TO-LOW
TRANSITIONS (ST IS ACTIVATED BY FALLING EDGES ONLY) WHICH
WILL KEEP THE WATCHDOG TIMER FROM FORCING THE RESET
OUTPUTS ACTIVE FOR A TIME OF tRST. tTD IS A FUNCTION OF THE
VOLTAGE AT THE TD PIN, AS TABULATED BELOW.
CONDITON
MIN
TYP
MAX
TD PIN = 0V
TD PIN = OPEN
TD PIN = VCC
62.5msec
150msec
250msec
250msec
600msec
1000msec
500msec
1200msec
2000msec
t
TD
PUSH-BUTTON RESET
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