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Электронный компонент: TC14433EPG

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3-127
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC14433
TC14433A
3-1/2 DIGIT A/D CONVERTERS
APPLICATIONS
s
Portable Instruments
s
Digital Voltmeters
s
Digital Panel Meters
s
Digital Scales
s
Digital Thermometers
s
Remote A/D Sensing Systems
s
MPU Systems
s
See Application Notes 19 and 21
TC14433/A-6 10/21/96
FEATURES
s
Accuracy ...................
0.05% of Reading
1 Count
s
Two Voltage Ranges ............. 1.999V and 199.9 mV
s
Up to 25 Conversions Per Second
s
Z
IN
> 1000M Ohms
s
Single Positive Voltage Reference
s
Auto-Polarity and Auto-Zero
s
Overrange and Underrange Signals Available
s
Operates in Auto-Ranging Circuits
s
Uses On-Chip System Clock or External Clock
s
Wide Supply Range .................... e.g.,
4.5V to
8V
s
Package Available .................................. 24-Pin DIP
24-Pin CerDIP, 28-Pin SOIC and 28-Pin PLCC
GENERAL DESCRIPTION
The TC14433 is a low power, high-performance, mono-
lithic CMOS 3-1/2 digit A/D converter. The TC14433 com-
bines both analog and digital circuits on a single IC, thus
minimizing the number of external components. This dual-
slope A/D converter provides automatic polarity and zero
correction with the addition of two external resistors and two
capacitors. The full-scale voltage range of this ratiometric IC
extends from 199.9 millivolts to 1.999 volts. The TC14433
can operate over a wide range of power supply voltages,
including batteries and standard 5-volt supplies.
The TC14433 will interface with the TC7211A LCD
display driver.
The TC14433A features improved performance over
the industry standard TC14433. Rollover, which is the
measurement of identical positive and negative signals, is
guaranteed to have the same reading within one count for
the TC14433A. Power consumption of the TC14433A is
typically 4 mW, approximately one-half that of the industry
standard TC14433.
ORDERING INFORMATION
Part No.
Package
Temp.Range
TC14433AEJG
24-Pin CerDIP
40
C to +85
C
TC14433AELI
28-Pin PLCC
40
C to +85
C
TC14433AEPG
24-Pin Plastic DIP
40
C to +85
C
TC14433COG
24-Pin SOIC
0
C to +70
C
TC14433EJG
24-Pin CerDIP
40
C to +85
C
TC14433ELI
28-Pin PLCC
40
C to +85
C
TC14433EPG
24-Pin Plastic DIP
40
C to +85
C
FUNCTIONAL BLOCK DIAGRAM
LATCHES
1'S
10'S
100'S
1,000'S
CLOCK
R
C
CONTROL
LOGIC
CMOS
ANALOG
SUBSYSTEM
DISPLAY
UPDATE
9
DU
END OF
CONVERSION
EOC
R
1
C
1
/
14
R
1
C
1
4
5
6
CO
1
CO
2
7
8
2
1
3
V
REF
V
AG
V
X
REFERENCE VOLTAGE
ANALOG GROUND
ANALOG INPUT
V
DD
V
SS
V
EE
= PIN 24
= PIN 13
= PIN 12
OFFSET
POLARITY DETECT
10
CLK1
11
CLK0
OR
OVERRANGE
MULTIPLEXER
2023
1619
DS
DIGIT STROBE
1
DS
4
Q
BCD DATA
0
Q
3
INTEGRATOR
15
OVERFLOW
3-128
TELCOM SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS:
V
DD
= +5V, V
EE
= 5V, C
1
= 0.1
F (mylar), C
O
= 0.1
F, R
C
= 300k
, R
1
=
470k
@ V
REF
= 2V, R
1
= 27k
@ V
REF
= 200mV, unless otherwise specified.
T
A
= +25
C
40
C < T
A
< +85
C
Symbol Parameter
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Analog Input
SYE
Rollover Error (Positive
200mV Full Scale V
IN
1
--
+1
--
--
--
Counts
and Negative Full
V
IN
= +V
IN
Scale Symmetry
NL
Linearity Output
V
REF
= 2V
0.05
+0.05
+0.05
--
--
--
%rdg
Reading (Note 1)
V
REF
= 200mV
1 count
--
+1 count
--
--
--
SOR
Stability Output Reading
V
X
= 1.99V, V
REF
= 2V
--
--
2
--
--
--
LSD
(Note 2)
V
X
= 199mV, V
REF
= 200mV
--
--
3
--
--
--
ZOR
Zero Output Reading
V
X
= 0V, V
REF
= 2V
--
0
0
--
--
--
LSD
I
IN
Bias Current:
Analog Input
--
20
100
--
--
--
pA
Reference Input
--
20
100
--
--
--
Analog Ground
--
20
500
--
--
--
CMRR
Common-Mode Rejection V
X
= 1.4V, V
REF
= 2V,
--
65
--
--
--
--
dB
f
OC
= 32kHz
Digital
V
OL
Output Voltage
V
SS
= 0V,
"0" Level
--
0
0.05
--
--
0.05
V
Pins 14 to 23 (Note 3)
V
SS
= 5V,
"0" Level
--
5
4.95
--
--
4.95
V
OH
Output Voltage
V
SS
= 0V,
"1" Level
4.95
5
--
4.95
--
--
V
Pins 14 to 23 (Note 3)
V
SS
= 5V,
"1" Level
4.95
5
--
4.95
--
--
I
OH
Output Current
V
SS
= 0V, V
OH
= 4.6V Source
0.2
0.36
--
0.14
--
--
mA
Pins 14 to 23
V
SS
= 5V, V
OH
= 5V Source
0.5
0.9
--
0.35
--
--
I
OL
Output Current
V
SS
= 0V, V
OL
= 0.4V Sink
0.51
0.88
--
0.36
--
--
mA
Pins 14 to 23
V
SS
= 5V, V
OL
= 4.5V Sink
1.3
2.25
--
0.9
--
--
f
CLK
Clock Frequency
R
C
= 300k
--
66
--
--
--
--
kHz
I
DU
Input Current DU
--
0.00001
0.3
--
--
1
A
Power
I
Q
Quiescent Current
V
DD
to V
EE
, I
SS
= 0, 14433A:
V
DD
= 5, V
EE
= 5
--
0.4
2
--
--
3.7
mA
V
DD
= 8, V
EE
= 8
--
1.4
4
--
--
7.4
V
DD
to V
EE
, I
SS
= 0, 14433:
V
DD
= 5, V
EE
= 5
--
0.9
2
--
--
3.7
V
DD
= 8, V
EE
= 8
--
1.8
4
--
--
7.4
PSRR
Supply Rejection
V
DD
to V
EE
, I
SS
= 0, V
REF
= 2V
--
0.5
--
--
--
--
mV/V
V
DD
= 5, V
EE
= 5
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
DD
V
EE
) ...................... 0.5V to +18V
Voltage on Any Pin,
Reference to V
EE
....................... 0.5V to (V
DD
+ 0.5)
DC Current, Any Pin ..............................................
10mA
Operating Temperature Range ............... 40
C to +85
C
Power Dissipation (T
A
< 70
C)
Plastic PLCC ....................................................... 1.0W
Plastic DIP ....................................................... 940mW
SOIC ................................................................ 940mW
CerDIP ............................................................... 1.45W
Storage Temperature Range ................ 65
C to +160
C
Lead Temperature (Soldering, 10 sec) ................. +300
C
*This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operation sections of
the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
3-129
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
PIN CONFIGURATIONS
1
2
3
4
16
15
14
5
6
7
8
13
19
18
17
9
10
11
12
20
21
22
23
24 VDD
Q3
Q2
Q1
Q0
DS1
DS3
DS2
DS4
V
REF
NC
V
DD
Q
3
Q1
Q0
DS2
DS3
DS1
DS4
Q
2
V
AG
V
X
EOC
OR
R1
C1
CO1
CO1
V
EE
CO2
CO2
R1/C1
R1/C1
C1
R1
V
SS
EOC
OR
NC
NC
NC
DU
CLK0
CLK1
CLK0
CLK1
DU
VEE
VSS
VAG
VX
V
REF
TC14433AEPG
TC14433EPG
TC14433AEJG
TC14433EJG
(PDIP)
(CerDIP)
1
2
3
4
16
15
14
5
6
7
8
13
19
18
17
9
10
11
12
20
21
22
23
24 VDD
Q3
Q2
Q1
Q0
DS1
DS3
DS2
DS4
EOC
OR
R1
C1
CO1
CO2
R1/C1
CLK0
CLK1
DU
VEE
VSS
VAG
VX
V
REF
TC14433COG
(SOIC)
19
20
21
22
23
24
25
11
10
9
8
7
6
5
TC14433AELI
TC14433ELI
(PLCC)
12 13
14 15
17
18
4
3
2
1
27
26
28
16
NOTES: 1. Accuracy -- The accuracy of the meter at full-scale is the accuracy of the setting of the reference voltage. Zero is recalculated during
each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other
than positive full-scale and zero is defined as the linearity specification.
2. The LSD stability for 200mV scale is defined as the range that the LSD will occupy 95% of the time.
3. Pin numbers refer to 24-pin DIP.
3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
3-130
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
PIN DESCRIPTIONS
Pin No.
Pin No.
Pin No.
24-Pin
24-Pin
28-Pin
PDIP/CerDip
SOIC
PLCC
Symbol
Description
1
1
2
V
AG
This is the analog ground; it has a high input impedance -- This pin
determines the reference level for the unknown input voltage (V
X
) and the
reference voltage (V
REF
).
2
2
3
V
REF
Reference voltage -- Full-scale output is equal to the voltage applied to
V
REF
. Therefore, full-scale voltage of 1.999V requires 2V reference and
199.9 mV full-scale requires a 200 mV reference. V
REF
functions as system
reset also. When switched to V
EE
, the system is reset to the beginning of
the conversion cycle.
3
3
4
V
X
The unknown input voltage (V
X
) is measured as a ratio of the reference
voltage (V
REF
) in a ratiometric A/D conversion.
4
4
5
R
1
These pins are for external components used for the integration function in
the dual slope conversion. Typical values are 0.1
F (mylar) capacitor for C
1
.
5
5
6
R
1
/C
1
R
1
= 470 kW (resistor) for 2V full-scale.
6
6
7
C
1
R
1
= 27 kW (resistor) for 200 mV full-scale. Clock frequency of 66 kHz gives
250 msec conversion time. See equation below for calculation of integrator
component values.
7
7
9
CO
1
These pins are used for connecting the offset correction capacitor. The
8
8
10
CO
2
recommended value is 0.1
F.
9
9
11
DU
Display update input pin -- When DU is connected to the EOC output every
conversion is displayed. New data will be strobed into the output latches
during the conversion cycle if a positive edge is received on DU prior to the
ramp-down cycle. When this pin is driven from an external source, the
voltage should be referenced to V
SS
.
10
10
12
CLK
1
Clock input pins -- The TC14433 has its own oscillator system clock.
Connecting a single resistor between CLK
1
and CLK
0
sets the clock frequency.
11
11
13
CLK
0
A crystal or OC circuit may be inserted in lieu of a resistor for improved
CLK
1
, the clock input, can be driven from an external clock source,
which need only have standard CMOS output drive. This pin is referenced to
V
EE
for external clock inputs. A 300 kW resistor yields a clock frequency of
about 66 kHz. (See typical characteristic curves; see Figure 9 for alternate
circuits.)
12
12
14
V
EE
Negative power current -- Connection pin for the most negative supply. Please
note the current for the output drive circuit is returned through V
SS
. Typical
supply current is 0.8 mA.
13
13
16
V
SS
Negative power supply for output circuitry -- This pin sets the low voltage level
for the output pins (BCD, Digit Selects, EOC, OR). When connected to analog
ground, the output voltage is from analog ground to V
DD
. If connected to V
EE
,
the output swing is from V
EE
to V
DD
. The recommended operating range for
V
SS
is between the V
DD
3 volts and V
EE
.
14
14
17
EOC
End of conversion output generates a pulse at the end of each conversion
cycle. This generated pulse width is equal to one-half the period of the system
clock.
15
15
18
OR
Overrange pin -- Normally this pin is set high. When V
X
exceeds V
REF
the OR
pin is low.
3-131
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
PIN DESCRIPTIONS (Cont.)
Pin No.
Pin No.
Pin No.
24-Pin
24-Pin
28-Pin
PDIP/CerDip
SOIC
PLCC
Symbol
Description
16
16
19
DS
4
Digit select pins -- The digit select output goes high when the respective digit
is selected. The MSD (1/2 digit) turns on immediately after an EOC pulse.
17
17
20
DS
3
The remaining digits turn on in sequence from MSD to LSD.
18
18
21
DS
2
To ensure that the BCD data has settled, an inter-digit blanking time of two
clock periods is included.
19
19
23
DS
1
Clock frequency divided by 80 equals multiplex rate. For example, a system
clock of 60 kHz gives a multiplex rate of 0.8 kHz.
20
20
24
Q
0
See Figure 12 for digit select timing diagram.
21
21
25
Q
1
BCD data output pins -- Multiplexed BCD outputs contain three full digits of
information during digit select DS
2
, DS
3
, DS
4
.
22
22
26
Q
2
During DS
1
, the 1/2 digit, overrange, underrange and polarity information is
available.
23
23
28
Q
3
Refer to truth table.
24
24
28
V
DD
Positive power supply -- This is the most positive power supply pin.
8,15, 22
NC
Not Used.
CIRCUIT DESCRIPTION
The TC14433 CMOS IC becomes a modified dual-
slope A/D with a minimum of external components. This IC
has the customary CMOS digital logic circuitry, as well as
CMOS analog circuitry. It provides the user with digital
functions (such as counters, latches, multiplexers) and
analog functions (such as operational amplifiers and com-
parators) on a single chip.
Features of this system include auto-zero, high input
impedances and auto-polarity. Low power consumption
and a wide range of power supply voltages are also advan-
tages of this CMOS device. The system's auto-zero function
compensates for the offset voltage of the internal amplifiers
and comparators. In this "ratiometric system," the output
reading is the ratio of the unknown voltage to the reference
voltage, where a ratio of 1 is equal to the maximum count of
1999. It takes approximately 16,000 clock periods to com-
plete one conversion cycle. Each conversion cycle may be
divided into 6 segments. Figure 7 shows the conversion
cycle in 6 segments for both positive and negative inputs.
Segment 1 -- The offset capacitor (C
O
), which com-
pensates for the input offset voltages of the buffer and
integrator amplifiers, is charged during this period. How-
ever, the integrator capacitor is shorted. This segment
requires 4000 clock periods.
Segment 2 -- During this segment, the integrator
output decreases to the comparator threshold voltage. At
this time, a number of counts equivalent to the input offset
Figure 7. Integrator Waveforms at Pin 6
Figure 8. Equivalent Circuit Diagrams of the Analog
Section During Segment 4 of the Timing Cycle
START
1
2
3
4
5
6
TYPICAL
POSITIVE
INPUT
VOLTAGE
TYPICAL
NEGATIVE
INPUT
VOLTAGE
TIME
SEGMENT
NUMBER
END
V
X
V
X
C
1
COMPARATOR
R
1
V
X
BUFFER
INTEGRATOR
+
+
+
voltage of the comparator is stored in the offset latches for
later use in the auto-zero process. The time for this segment
is variable and less than 800 clock periods.