Document Outline
- Return to Contents
- List of Figures
- 1. Test Circuit
- 2. Digital Logic Input
- 3A. Internal Analog Switches
- 3B. System Zero Phase
- 3C. Input Signal Integration Phase
- 3D. Reference Voltage Integration Phase
- 3E. Integrator Output Zero Phase
- 4. Basic Dual-Slope Converter
- 5. Using an External Reference Voltage
- 6. Digital Section Functional Diagram
- 7. Timing Diagrams for Outputs
- 8. Strobe Signal Pulses Low Five Times per Conversion
- 9. Negative Supply Voltage Generator
- List of Tables
- 1. Internal Analog Gate Status
- 2. Line Frequency Rejection
- 3. Conversion Rate vs Clock Frequency
- Features
- Typical 4-1/2 Digit DVM with LCD
- General Description
- Ordering Information
- Absolute Maximum Ratings
- Electrical Chracteristics
- Pin Configurations
- General Theory of Operation
- Dual-Slope Conversion Principles
- TC7135 Operational Theory
- Analog Section Functional Description
- Digital Section Functional Description
- Applications Information
- Component Value Selection
- Conversion Timing
- Displays and Driver Circuits
- High-Speed Operation
- Zero-Crossing Flip-Flop
- Generating a Negative Supply
- Typical Applications
3-113
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
GENERAL DESCRIPTION
The TC7135 4-1/2 digit analog-to-digital converter (ADC)
offers 50 ppm (1 part in 20,000) resolution with a maximum
nonlinearity error of 1 count. An auto-zero cycle reduces zero
error to below 10
V and zero drift to 0.5
V/
C. Source
impedance errors are minimized by a 10 pA maximum input
current. Roll-over error is limited to
1 count.
By combining the TC7135 with a TC7211A (LCD) or
TC7212A (LED) driver, a 4-1/2 digit display DVM or DPM can
be constructed. Overrange and underrange signals support
automatic range switching and special display blanking/flash-
ing applications.
Microprocessor-based measurement systems are sup-
ported by BUSY, STROBE, and RUN/HOLD control signals.
Remote data acquisition systems with data transfer via UARTs
are also possible. The additional control pins and multiplexed
BCD outputs make the TC7135 the ideal converter for dis-
play or microprocessor-based measurement systems.
TC7135
ORDERING INFORMATION
Temperature
Part No.
Package
Range
TC7135CBU
64-Pin Plastic
0
C to +70
C
Flat Package
TC7135CLI
28-Pin PLCC
0
C to +70
C
TC7135CPI
28-Pin Plastic DIP
0
C to +70
C
TC7135
5V
V
REF IN
ANALOG
COMMON
UR
OR
STROBE
RUN/HOLD
DGND
POL
CLOCK
BUSY
D1
D2
D3
0.1 F
0.47 F
1 F
ANALOG
GROUND
100 k
0.1
F
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
28
27
26
25
24
23
22
21
20
19
TC04
+5V
1/4 CD4030
CLOCK IN
+5V
BP
D
D
D
D
1
2
3
4
4-1/2 DIGIT LCD
SEGMENT
D
R
I
V
E
5
31
32
33
34
30
29
28
27
TC7211A
SEG
OUT
OSC
GND
36
+5V
+5V
1
CD4081
1 16 15 14 12 5 3 4
7 8 13 11 10 9 2 6
CD4054A
OPTIONAL
CAP
35
15
120 Hz = 3 READING/SEC
BACKPLANE
B
B
B
B
3
2
1
0
D4
B8
B4
18
17
16
100 k
100 k
6.8 k
1 F
INT OUT
AZ IN
BUFF OUT
CREF
CREF
INPUT
+INPUT
V
D5
B1
B2
+
V
+
2,3,4
626
3740
+
+5V
FEATURES
s
Low Roll-Over Error .........................
1 Count Max
s
Guaranteed Nonlinearity Error ........
1 Count Max
s
Guaranteed Zero Reading for 0V Input
s
True Polarity Indication at Zero for Null Detection
s
Multiplexed BCD Data Output
s
TTL-Compatible Outputs
s
Differential Input
s
Control Signals Permit Interface to UARTs and
Processors
s
Auto-Ranging Supported With Overrange and
Underrange Signals
s
Blinking Display Visually Indicates Overrange
Condition
s
Low Input Current ............................................. 1 pA
s
Low Zero Reading Drift ............................... 2
V/
C
s
Interfaces to TC7211A (LCD) and TC7212A (LED)
Display Drivers
s
Available in DIP and Surface-Mount Packages
TYPICAL 4-1/2 DIGIT DVM WITH LCD
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
TC7135-10 11/6/96
3-114
TELCOM SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS:
T
A
= +25
C, f
CLOCK
= 120 kHz, V
+
= +5V, V
= 5V (Figure 1)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Analog
Display Reading With
Notes 2 and 3
0.0000
0.0000
+0.0000
Display
Zero Volt Input
Reading
TC
Z
Zero Reading Temperature
V
IN
= 0V
--
0.5
2
V/
C
Coefficient
Note 4
TC
FS
Full-Scale Temperature
V
IN
= 2V
--
--
5
ppm/
C
Coefficient
Notes 4 and 5
NL
Nonlinearity Error
Note 6
--
0.5
1
Count
DNL
Differential Linearity Error
Note 6
--
0.01
--
LSB
Display Reading in
V
IN
= V
REF
+0.9996
+0.9999
+1.0000
Display
Ratiometric Operation
Note 2
Reading
FSE
Full-Scale Symmetry
V
IN
= +V
IN
--
0.5
1
Count
Error (Roll-Over Error)
Note 7
I
IN
Input Leakage Current
Note 3
--
1
10
pA
V
N
Noise
Peak-to-Peak Value Not
--
15
--
V
P-P
Exceeded 95% of Time
Digital
I
IL
Input Low Current
V
IN
= 0V
--
10
100
A
I
IH
Input High Current
V
IN
= +5V
--
0.08
10
A
V
OL
Output Low Voltage
I
OL
= 1.6 mA
--
0.2
0.4
V
V
OH
Output High Voltage
B
1
, B
2
, B
4
, B
8
, D
1
D
5
I
OH
= 1 mA
2.4
4.4
5
V
Busy, Polarity, Overrange,
I
OH
= 10
A
4.9
4.99
5
V
Underrange, Strobe
f
CLK
Clock Frequency
Note 8
0
120
1200
kHz
Power Supply
V
+
Positive Supply Voltage
4
5
6
V
V
Negative Supply Voltage
3
5
8
V
I
+
Positive Supply Current
f
CLK
= 0 Hz
--
1
3
mA
I
Negative Supply Current
f
CLK
= 0 Hz
--
0.7
3
mA
PD
Power Dissipation
f
CLK
= 0 Hz
--
8.5
30
mW
NOTES:
1. Limit input current to under 100
A if input
voltages exceed supply voltage.
2. Full-scale voltage = 2V.
3. V
IN
= 0V.
4. 0
C
T
A
+70
C.
ABSOLUTE MAXIMUM RATINGS*
(Note 1)
Positive Supply Voltage ............................................. +6V
Negative Supply Voltage .............................................9V
Analog Input Voltage (Pin 9 or 10) ......... V
+
to V
(Note 2)
Reference Input Voltage (Pin 2) ........................... V
+
to V
Clock Input Voltage .............................................. 0V to V
+
Operating Temperature Range .................... 0
C to +70
C
Storage Temperature Range ................. 65
C to +160
C
Lead Temperature (Soldering, 10 sec) ................. +300
C
Package Power Dissipation (T
A
70
C)
Plastic DIP ........................................................ 1.14W
PLCC ................................................................ 1.00W
Plastic Flat Package ......................................... 1.14W
*Static-sensitive device. Unused devices must be stored in conductive
material to protect them from static discharge and static fields. Stresses
above those listed under "Absolute Maximum Ratings" may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
5. External reference temperature coefficient less than 0.01 ppm/
C.
6. 2V
V
IN
+2V. Error of reading from best fit straight line.
7. |V
IN
| = 1.9959.
8. Specification related to clock frequency range over which the
TC7135 correctly performs its various functions. Increased errors
result at higher operating frequencies.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3-115
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135CPI
(PDIP)
1
2
3
4
RUN/HOLD
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STROBE
OVERRANGE
B4
D3
D2
D1 (LSD)
BUSY
CLOCK IN
POLARITY
DIGTAL GND
UNDERRANGE
B2
(LSB) B1
(MSD) D5
V
+
+INPUT
INPUT
CREF
CREF
BUFF OUT
AZ IN
INT OUT
ANALOG
COM
REF IN
V
D4
B8 (MSB)
4
3
2
16
15
14
10
9
8
7
6
5
12
11
17
18 19 20 21
22 23 24 25
26
27 28
29 30 31
TC7135CBU
(PFP)
(NOTES 1)
NC
INT OUT
NC
AZ IN
NC
C
REF
NC
NC
C
REF
NC
INPUT
NC
+INPUT
NC
V
+
q
NOTES: 1. NC = No internal connection.
+
19
20
21
22
23
24
25
11
10
9
8
7
6
5
CLOCK IN
RUN/HOLD
TC7135CLI
(PLCC)
AZ IN
POLARITY
12 13
14 15
17
18
(MSD)
D5
(LSB)
B1
B2
B4
(MSB)
B8
D4
D3
DIGTAL GND
BUSY
D1 (LSD)
D2
BUFF OUT
REF CAP
REF CAP+
INPUT
V +
4
3
2
1
27
26
28
INT OUT
ANALOG
COM
REF IN
V
UR
OR
STROBE
16
+INPUT
32
BUFF OUT
NC
BUSY
D2
D1
63
61
60 59
58 57 56 55
54 53
52
51 50 49
64
NC
NC
NC
NC
NC
STROBE
RUN/HOLD
DGND
POL
NC
CLOCK IN
62
NC
NC
NC
NC
NC
NC
OVERRANGE
UNDERRANGE
NC
V
REF IN
ANALOG COM
NC
NC
NC
NC
NC
NC
D5
NC
NC
NC
NC
D3
NC
NC
D4
B8
B4
B2
NC
B1
NC
13
40
41
42
43
44
45
46
34
35
36
37
38
39
33
48
47
1
+
PIN CONFIGURATIONS
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3-116
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
Figure 3A. Internal Analog Switches
Figure 1. Test Circuit
Figure 2. Digital Logic Input
Figure 3D. Reference Voltage Integration Phase
Figure 3C. Input Signal Integration Phase
Figure 3B. System Zero Phase
TC7135
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
100 k
ANALOG GND
100
k
SIGNAL
INPUT
0.1 F
SET VREF = 1V
V
REF IN
ANALOG
COMMON
INT OUT
AZ IN
BUFF OUT
CREF
CREF
INPUT
+INPUT
D5 (MSD)
B1 (LSB)
B2
V
+
UNDERRANGE
OVERRANGE
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
(LSD) D1
D2
D4
(MSB) B8
B4
D3
+5V
1 F
100 k
1 F
0.47
F
VREF IN
CLOCK
INPUT
120 kHz
5V
+
+
+
+
+ IN
IN
REF
ANALOG
COM
IN
SWI
SWR
SWZ
SWI
SW1
SWZ
SWIZ
SWZ
INTEGRATOR
ANALOG
INPUT BUFFER
SW RI
+
SWRI
COMPARATOR
TO
DIGITAL
SECTION
SW RI
+
SWRI
RINT
CINT
CREF
CSZ
BUFFER
LOGIC
INPUT
V
+
+
+
+
+ IN
IN
REF
ANALOG
COM
IN
SWI
SWR
SWZ
SWI
SW1
SWZ
SWIZ
SWZ
INTEGRATOR
SWITCH CLOSED
SWITCH OPEN
SW RI
+
SWRI
COMPARATOR
TO
DIGITAL
SECTION
SW RI
+
SWRI
ANALOG
INPUT BUFFER
RINT
CINT
CREF
CSZ
+
+
+
+ IN
IN
REF
ANALOG
COM
IN
SWI
SWR
SWZ
SWI
SW1
SWZ
SWIZ
SWZ
INTEGRATOR
SWITCH CLOSED
SWITCH OPEN
SW RI
+
SWRI
COMPARATOR
TO
DIGITAL
SECTION
SW RI
+
SWRI
ANALOG
INPUT BUFFER
RINT
CINT
CREF
CSZ
+
+
+
+ IN
IN
REF
ANALOG
COM
IN
SWI
SWR
SWZ
SWI
SW1
SWZ
SWIZ
SWZ
INTEGRATOR
SWITCH CLOSED
SWITCH OPEN
SW RI
+
SWRI
COMPARATOR
TO
DIGITAL
SECTION
SW RI
+
SWRI
ANALOG
INPUT BUFFER
RINT
CINT
CREF
CSZ
3-117
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to 28-Pin DIP)
Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating analog-to-
digital converter. An understanding of the dual-slope con-
version technique will aid in following detailed TC7135
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo-
site polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "ramp-
down."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
For a constant V
IN
:
V
IN
= V
R
.
Figure 4. Basic Dual-Slope Converter
Figure 3E. Integrator Output Zero Phase
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
(See Figure 4.)
TC7135 Operational Theory
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
The TC7135 measurement cycle contains four phases:
(1) System zero
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
Internal analog gate status for each phase is shown in
Table 1.
t
RI
t
SI
[ ]
where:
V
R
= Reference voltage
t
SI
= Signal integration time (fixed)
t
RI
= Reference voltage integration time (variable).
1
V
R
t
RI
RC
RC
V
IN
(t) dt = ,
t
SI
0
+
+
+
+ IN
IN
REF
ANALOG
COM
IN
SWI
SWR
SWZ
SWI
SW1
SWZ
SWIZ
SWZ
INTEGRATOR
SWITCH CLOSED
SWITCH OPEN
SW RI
+
SWRI
COMPARATOR
TO
DIGITAL
SECTION
SW RI
+
SWRI
ANALOG
INPUT BUFFER
RINT
CINT
CREF
CSZ
+
REF
VOLTAGE
ANALOG
INPUT
SIGNAL
+
DISPLAY
SWITCH
DRIVER
CONTROL
LOGIC
INTEGRATOR
OUTPUT
CLOCK
COUNTER
POLARITY CONTROL
PHASE
CONTROL
VIN
VIN
VFULL SCALE
1/2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
COMPARATOR
3-118
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
Table 1. Internal Analog Gate Status
Conversion
Reference
Cycle Phase
SW
I
SW
R
+
SW
R
SW
Z
SW
R
SW
1
SW
IZ
Schematic
System Zero
Closed
Closed
Closed
3B
Input Signal
Closed
3C
Integration
Reference Voltage
Closed*
Closed
3D
Integration
Integrator
Closed
Closed
3E
Output Zero
*NOTE: Assumes a positive polarity input signal. SW
R
would be closed for a negative input signal.
Internal Analog Gate Status
System Zero Phase
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by charg-
ing C
AZ
(auto-zero capacitor) with a compensating error
voltage. With zero input voltage, the integrator output re-
mains at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SW
I
switches. The
internal input points connect to analog common. The refer-
ence capacitor charges to the reference voltage potential
through SW
R
. A feedback loop, closed around the integrator
and comparator, charges the C
AZ
with a voltage to compen-
sate for buffer amplifier, integrator, and comparator offset
voltages. (See Figure 3B.)
Analog Input Signal Integration Phase
The TC7135 integrates the differential voltage between
the +INPUT and INPUT. The differential voltage must be
within the device's common-mode range; 1V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase. (See Figure 3C.)
Reference Voltage Integration Phase
The previously-charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero. (See Figure 3D.) The digital reading
displayed is:
Reading = 10,000
.
Integrator Output Zero Phase
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
condition exists, the phase is extended to 6200 clock cycles.
(See Figure 3E.)
Differential Input
V
REF
Analog Section Functional Description
Differential Inputs
The TC7135 operates with differential voltages (+IN-
PUT, pin 10 and INPUT, pin 9) within the input amplifier
common-mode range which extends from 1V below the
positive supply to 1V above the negative supply. Within this
common-mode voltage range, an 86 dB common-mode
rejection ratio is typical.
The integrator output also follows the common-mode
voltage and must not be allowed to saturate. A worst-case
condition exists, for example, when a large positive com-
mon-mode voltage with a near full-scale negative differential
input voltage is applied. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common-mode voltage. For these critical
applications, the integrator swing can be reduced to less
than the recommended 4V full-scale swing, with some loss
of accuracy. The integrator output can swing within 0.3V of
either supply without loss of linearity.
Analog Common
ANALOG COMMON (pin 3) is used as the INPUT
return during the auto-zero and deintegrate phases. If
INPUT is different from analog common, a common-mode
voltage exists in the system. This signal is rejected by the
excellent CMRR of the converter. In most applications,
INPUT will be set at a fixed known voltage (power supply
common, for instance). In this application, analog common
should be tied to the same point, thus removing the common-
mode voltage from the converter. The reference voltage is
referenced to analog common.
Reference Voltage
The reference voltage input (REF IN, pin 2) must be a
positive voltage with respect to analog common. Two refer-
ence voltage circuits are shown in Figure 5.
[
]
3-119
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
Digital Section Functional Description
The major digital subsystems within the TC7135 are
illustrated in Figure 6, with timing relationships shown in
Figure 7. The multiplexed BCD output data can be displayed
on an LCD with the TC7211A.
The digital section is best described through a discus-
sion of the control signals and data outputs.
RUN/HOLD Input
When left open, the RUN/HOLD (R/H) input (pin 25)
assumes a logic "1" level. With R/H = 1, the TC7135
performs conversions continuously, with a new measure-
ment cycle beginning every 40,002 clock pulses.
When R/H changes to logic "0," the measurement cycle
in progress will be completed, and data held and displayed,
as long as the logic "0" condition exists.
A positive pulse (>300nsec) at R/H initiates a new
measurement cycle. The measurement cycle in progress
when R/H initially assumed logic "0" must be completed
before the positive pulse can be recognized as a single
conversion run command.
The new measurement cycle begins with a 10,001-
count auto-zero phase. At the end of this phase, the busy
signal goes high.
Figure 6. Digital Section Functional Diagram
Figure 5. Using an External Reference Voltage
LATCH
LATCH
LATCH
LATCH
LATCH
COUNTERS
CONTROL LOGIC
MULTIPLEXER
POLARITY
D5
D4
D3
D2
D1
13 B1
14 B2
15 B4
16 B8
POLARITY
FF
MSB
DIGIT
DRIVE
SIGNAL
LSB
DATA
OUTPUT
24
22
25
27
28
26
21
DIGITAL
GND
CLOCK
IN
RUN/
HOLD
OVER
RANGE
STROBE
BUSY
UNDER
RANGE
ZERO
CROSS
DETECT
FROM
ANALOG
SECTION
20
k
6.8 k
V+
1.25V REF
TC04
V+
REF
IN
2.5V
REF
V+
I
REF
TC7135
V
V+
ANALOG
GROUND
ANALOG
COMMON
REF
IN
TC7135
ANALOG
COMMON
TC05
3-120
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
Figure 7. Timing Diagrams for Outputs
The active-low STROBE pulses aid BCD data transfer
to UARTs, microprocessors, and external latches. (See
Application Note AN-16.)
BUSY Output
At the beginning of the signal-integration phase, BUSY
(pin 21) goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to logic "0"
after the measurement cycle ends in an overrange condi-
tion. The internal display latches are loaded during the first
clock pulse after BUSY and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
phase.
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVERRANGE
output (pin 27) is set to logic "1." The OVERRANGE output
register is set when BUSY goes low and reset at the
beginning of the next reference-integration phase.
UNDERRANGE Output
If the output count is 9% of full scale or less (
1800
counts), the UNDERRANGE output (pin 28) register bit is
set at the end of BUSY. The bit is set low at the next signal-
integration phase.
STROBE Output
During the measurement cycle, the STROBE output
(pin 26) control line is pulsed low five times. The five low
pulses occur in the center of the digit drive signals (D
1
, D
2
,
D
3
, D
4
and D
5
; see Figure 8).
D
5
goes high for 201 counts when the measurement
cycles end. In the center of D
5
pulse, 101 clock pulses after
the end of the measurement cycle, the first STROBE occurs
for one-half clock pulse. After D
5
strobe, D
4
goes high for 200
clock pulses. STROBE goes low 100 clock pulses after D
4
goes high. This continues through the D
1
drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
,
,
INTEGRATOR
OUTPUT
OVERRANGE
WHEN
APPLICABLE
UNDERRANGE
WHEN
APPLICABLE
SYSTEM
ZERO
10,001
COUNTS
SIGNAL
INTE
10,000
COUNTS
(FIXED)
REFERENCE
INTEGRATE
20,001
COUNTS (MAX)
FULL MEASUREMENT CYCLE
40,002 COUNTS
BUSY
EXPANDED SCALE
BELOW
D5
D4
D3
D2
D1
100
COUNTS
DIGIT SCAN
STROBE
AUTO ZERO
SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
D5
D4
D3
D2
D1
DIGIT SCAN
FOR
OVERRANGE
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
*
*
*
END OF CONVERSION
D5 (MSD)
DATA
BUSY
B1B8
STROBE
D5
D4
D3
D2
D1
D4
DATA
D3
DATA
D2
DATA
D1 (LSD)
DATA
D5
DATA
NOTE ABSENCE
OF STROBE
201
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
*
*
DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
TC7135
OUTPUTS
3-121
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
POLARITY Output
A positive input is registered by a logic "1" polarity signal.
The POLARITY output (pin 23) is valid at the beginning of
reference integrate and remains valid until determined dur-
ing the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null applica-
tions.
Digit Drive Outputs
Digit drive outputs are positive-going signals. Their scan
sequence is D
5
, D
4
, D
3
, D
2
and D
1
(pins 12, 17, 18, 19 and
20, respectively). All positive signals are 200 clock pulses
wide, except D
5
, which is 201 clock pulses.
All five digits are continuously scanned, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated, providing a blinking
visual display.
BCD Data Outputs
The binary coded decimal (BCD) outputs, B
8
, B
4
, B
2
and
B
1
(pins 16, 15, 14 and 13, respectively) are positive true-
logic signals. They become active simultaneously with digit
drive signals. In an overrange condition, all data bits are
logic "0".
APPLICATIONS INFORMATION
Component Value Selection
Integrating Resistor
The integrating resistor (R
INT
) is determined by the full-
scale input voltage and output current of the buffer used to
charge the integrator capacitor (C
INT
). Both the buffer ampli-
fier and the integrator have a Class A output stage, with 100
A of quiescent current. A 20
A drive current gives negli-
gible linearity errors. Values of 5
A to 40
A give good
results. The exact value of R
INT
for a 20
A current is easily
calculated:
R
INT
=
.
Full-scale voltage
20
A
Integrating Capacitor
The product of R
INT
and C
INT
should be selected to give
the maximum voltage swing to ensure tolerance build-up will
not saturate integrator swing (approximately 0.3V from
either supply). For
5V supplies, and analog common tied to
supply ground, a
3.5V to
4V full-scale integrator swing is
C
INT
=
=
.
[10,000 x clock period] x I
INT
Integrator output voltage swing
(10,000) (clock period) (20
A)
Integrator output voltage swing
Conversion Timing
Line Frequency Rejection
A signal-integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 100 kHz clock frequency will reject 50 Hz, 60 Hz and
400 Hz noise, corresponding to 2.5 readings per second.
A very important characteristic of the C
INT
is that it has
low dielectric absorption to prevent roll-over or ratiometric
errors. A good test for dielectric absorption is to use the
capacitor with the input tied to the reference. This ratiometric
condition should read half-scale 0.9999. Any deviation is
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor (C
AZ
) has some
influence on system noise. A large capacitor reduces noise.
The reference capacitor (C
REF
) should be large enough
such that stray capacitance from its nodes to ground is
negligible.
The dielectric absorption of C
REF
and C
AZ
is only impor-
tant at power-on, or when the circuit is recovering from an
overload. Smaller or cheaper capacitors can be used if
accurate readings are not required during the first few
seconds of recovery.
Reference Voltage
The analog input required to generate a full-scale output
is V
IN
= 2 V
REF
.
The stability of the reference voltage is a major factor in
overall absolute accuracy of the converter. Therefore, it is
recommended that high-quality references be used where
high-accuracy, absolute measurements are being made.
Suitable references are:
Part Type
Manufacturer
TC04
TelCom Semiconductor
TC05
TelCom Semiconductor
adequate. A 0.10
F to 0.47
F is recommended. In general,
the value of C
INT
is given by:
3-122
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
High-Speed Operation
The maximum conversion rate of most dual-slope ADCs
is limited by frequency response of the comparator. The
comparator in this circuit follows the integrator ramp with a
3
s delay, and at a clock frequency of 160 kHz (6
s period),
half of the first reference integrate clock period is lost in
delay. This means the meter reading will change from 0 to
1 with a 50
V input, 1 to 2 with 150
V, 2 to 3 with 250
V,
etc. This transition at midpoint is considered desirable by
most users; however, if clock frequency is increased appre-
ciably above 160 kHz, the instrument will flash "1" on noise
peaks even when the input is shorted.
For many dedicated applications, where the input signal
is always of one polarity, comparator delay need not be a
limitation. Since nonlinearity and noise do not increase
substantially with frequency, clock rates up to ~1 MHz may
be used. For a fixed clock frequency, the extra count (or
counts) caused by comparator delay will be constant and
can be digitally subtracted.
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage onto the
integrator output at the beginning of reference-integrate
phase. By careful selection of the ratio between this resis-
tor and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be com-
pensated for and maximum clock frequency extended
by approximately a factor of 3. At higher frequencies, ring-
ing and second-order breaks will cause significant
nonlinearities during the first few counts of the instrument.
The minimum clock frequency is established by leakage
on the auto-zero and reference capacitors. With most de-
vices, measurement cycles as long as 10 seconds give no
measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means if the display takes significant current from the logic
supply, the clock should have good PSRR.
Zero-Crossing Flip-Flop
The flip-flop interrogates data once every clock pulse
after transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by
clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
Table 3. Conversion Rate vs Clock Frequency
Conversion Rate
Clock
(Conv/Sec)
Frequency (kHz)
2.5
100
3.0
120
5.0
200
7.5
300
10.0
400
20.0
800
30.0
1200
Displays and Driver Circuits
TelCom Semiconductor manufactures three display de-
coder/driver circuits to interface the TC7135 to LCDs or LED
displays. Each driver has 28 outputs for driving four 7-
segment digit displays.
Device
Package
Description
TC7211AIPL
40-Pin Epoxy
4-Digit LCD Driver/Encoder
Several sources exist for LCDs and LED displays.
Display
Manufacturer
Address
Type
Hewlett Packard
640 Page Mill Road
LED
Components
Palo Alto, CA 94304
AND
720 Palomar Ave.
LCD and
Sunnyvale, CA 94086
LED
Epson America, Inc.
3415 Kanhi Kawa St.
LCD
Torrance, CA 90505
Table 2. Line Frequency Rejection
Oscillator Frequency
Frequency Rejected
(kHz)
(Hz)
300, 200, 150, 120,
60
100, 40, 33-1/3
250, 166-2/3,
50
125, 100
100
50, 60, 400
3-123
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zero gives an overload display of 0000 instead of 0001.
No delay occurs during signal integrate, so true ratiometric
readings result.
Generating a Negative Supply
A negative voltage can be generated from the positive
supply by using a TC7660. (See Figure 9.)
TC7660
TC7135
11
1
+5V
8
2
3
(5V)
V
+
V
24
10 F
5
4
10 F
+
+
Figure 9. Negative Supply Voltage Generator
TYPICAL APPLICATIONS
R2
R1
fO
GATES ARE 74C04
C
+5V
VOUT
390 pF
30 k
7
8
2
3
16 k
0.22
F
16 k
4
1 k
1
+5V
VOUT
2
3
1
4
7
6
R2
100 k
R2
100 k
R3
50 k
C2
10 pF
R4
2 k
C1
0.1
F
+
LM311
+
LM311
56 k
Comparator Clock Circuit
RC Oscillator Circuit
1. f
O
, R
P
=
a. If R = R
1
= R
2
, f
0.55/RC
b. If R
2
>> R
1
, f
0.45/R
1
C
c. If R
2
<<
R
1
, f
0.72/R
1
C
2. Examples:
a. f = 120 kHz, C = 420 pF
R
1
= R
2
10.9 k
b. f = 120 kHz, C = 420 pF, R
2
= 50 k
R
1
= 8.93 k
c. f = 120 kHz, C = 220 pF, R
2
= 5 k
R
1
= 27.3 k
1
2 C[0.41 R
P
+ 0.70 R
1
]
R
1
R
2
R
1
+ R
2
3-124
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TYPICAL APPLICATIONS (Cont.)
4-1/2 Digit ADC With Multiplexed Common Anode LED Display
20
19
18
17
12
23
7
8
16
15
14
13
11
2
1
3
9
10
22
6
5
4
6
2
1
7
5
915
16
b
c
7
7
7
7
TC7135
7447
BLANK MSD ON ZERO
D1
D2
D3
D4
D5
INT OUT
AZ IN
BUFF
OUT
fIN
+INPUT
INPUT
ANALOG
COMMON
V
REF
IN
POL
CREF
B8
B4
B2
B1
+5V
+5V
X7
0.47 F
120 kHz
+
ANALOG
INPUT
1 F
100 k
1 F
4.7 k
1 F
5V
100 k
100 k
6.8 k
D
B
C
A
RBI
V
+
CREF
+
TC04
TC04
TC7211A
TC7135
INT OUT
AZ IN
BUFF OUT
+INPUT
INPUT
ANALOG
COMMON
REF
IN
V
POL
V+
20
19
18
17
16
15
14
13
12
26
27
D1
D2
D3
D4
B8
B4
B2
B1
D5
STROBE
OR
5
31
32
33
34
30
29
28
27
V+
D1
D2
D3
D4
B1
BP
B3
B2
B0
GND
Q
R
S
D
CLK
CD4071
+5V
1/4 CD4030
4-1/2 DIGIT LCD
SEGMENT
DRIVE
1
35
+5V
+5V
5V
+
4
5
6
10
9
3
2
1/4 CD4081
1/2 CD4030
23
CD4081
1/4 CD4030
1/2
CD4013
6.8 k
100 k
100 k
100 k
0.47 F
1 F
ANALOG
INPUT
1
120 kHz
22
fIN
4-1/2 Digit ADC Interfaced to LCD With Digit Blanking on Overrange
3-125
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TYPICAL APPLICATIONS (Cont.)
4-1/2 Digit ADC With Multiplexed Common Cathode LED Display
TC04
28
27
26
25
24
23
22
21
9
8
7
6
5
4
3
2
1
REF IN
ANALOG
GND
INT
OUT
AZ IN
BUFF
OUT
CREF
+5V
5V
6.8V
UR
DGND
POLARITY
OR
STROBE
RUN/HOLD
CLK IN
BUSY
1
2
3
4
5
6
7
8
9
SET VREF = 1V
1.22V
100
k
ANALOG
GND
0.47 F
100 k
1 F
47
k
150
+5V
150
10
11
12
13
14
15
16
17
18
+5V
CD4513
BE
1 F
TC7135
20
19
18
17
16
15
INPUT
+INPUT
V
+
D5 (MSD)
B1 (LSB)
B2
(LSD) D1
D2
D3
D4
B4
(MSB) B8
10
11
12
13
14
100
k
SIG
IN
+
0.1
F
+5V
fO = 120 kHz
+
CREF
V
TC7135
DATA BUS
CONTROL
ADDRESS BUS
6522
-VIA-
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CA1
CA2
PB5
PB4
PB0
PB3
PB2
PB1
CHANNEL SELECTION
GAIN SELECTION
1Y
2Y
3Y
1B
2B
3B
SEL
1A
2A
3A
157
POL
OR
UR
D5
B8
B4
B2
B1
D1
D2
D3
D4
STB
R/H
V
+
REF
CAP
BUF
AZ
INT
INPUT
+
VR
INPUT
ANALOG
COMMON
DGND
5V
REF
VOLTAGE
10
14
16
15
8
11
3
9
GAIN: 10, 20, 50, 100
15V
15V
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
DIFFERENTIAL
MULTIPLEXER
DG529
DA
DB
WR
A1 A0 EN
5V
+
+
fIN
fIN
+
LH0084
4-Channel Data Acquisition System
PDF 
ZIP