THC63LVDM83R/THC63LVDM63R_Rev2.0
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 1 THine Electronics, Inc.
THC63LVDM83R/THC63LVDM63R
REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE
General Description
The THC63LVDM83R transmitter converts 28bits of
CMOS/TTL data into LVDS (Low Voltage Differential
Signaling) data stream. A phase-locked transmit clock
is transmitted in parallel with the data streams over a
fifth LVDS link. At a transmit clock frequency of
85MHz, 28bits of RGB data and 4bits of LCD timing
and control data (HSYNC, VSYNC, CNTL1, CNTL2)
are transmitted at a rate of 595Mbps per LVDS channel.
Also available is THC63LVDM63R that converts 21bits
of CMOS/TTL data into LVDS(Low Voltage Differen-
tial Signaling) data stream. Both transmitters can be
programmed reduced swing LVDS through a dedicated
pin for low power consumption and EMI.
Features
28:4 Data channel compression at up to
298 Megabytes per sec throughput
Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA
Narrow bus (10 lines or 8 lines) reduces cable size
Support Reduced swing LVDS for Low EMI
200mV swing LVDS/350mV swing LVDS
selectable
Support Spread Spectrum Clock Generator
On chip Input Jitter Filtering
PLL requires No external components
Single 3.3V supply with 125mW(TYP)
Power-Down Mode
Low profile 56 or 48 Lead TSSOP Package
Clock Edge Programmable
Improved Replacement for the National DS90C383
or DS90C363
Block Diagram
T
T
L
P
A
R
A
LL
EL
T
O
SE
R
I
A
L
PLL
TA +/-
TB +/-
TC +/-
TD +/-
TCLK +/-
R/F
/PDWN
TA0-6
TC0-6
TD0-6
TRANSMITTER
(20 to 85MHz)
CMOS/TTL
7
7
RS
7
TB0-6
7
INPUTS
CLOCK
(LVDS)
20-85MHz
DATA
(LVDS)
(140-595Mbit/On Each
LVDS Channel)
CLOCK IN
T
T
L
P
A
R
A
LL
EL
T
O
SE
R
I
A
L
PLL
7
7
7
CMOS/TTL
INPUTS
TA0-6
TB0-6
TC0-6
TRANSMITTER
(20 to 85MHz)
CLOCK IN
R/F
/PDWN
RS
TA +/-
TB +/-
TC +/-
TCLK +/-
CLOCK
(LVDS)
20-85MHz
(140-595Mbit/On Each
LVDS Channel)
THC63LVDM83R
THC63LVDM63R
DATA
(LVDS)
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 2 THine Electronics, Inc.
THC63LVDM83R /THC63LVDM63R_Rev2.0
Pin Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RS
TD1
TA5
TA6
GND
TB0
TB1
TD2
VCC
TD3
TB2
TB3
GND
TB4
TB5
TD4
R/F
TD5
TB6
TC0
GND
TC1
TC2
TC3
TD6
VCC
TC4
TC5
TA4
TA3
TA2
GND
TA1
TA0
TD0
LVDS GND
TA-
TA+
TB-
TB+
LVDS VCC
LVDS GND
TC-
TC+
TCLK-
TCLK+
TD-
TD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLK IN
TC6
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RS
TA5
TA6
GND
TB0
TB1
VCC
TB2
TB3
GND
TB4
TB5
R/F
TB6
TC0
GND
TC1
TC2
TC3
VCC
TC4
TC5
TA4
TA3
TA2
GND
TA1
TA0
LVDS GND
TA-
TA+
TB-
TB+
LVDS VCC
LVDS GND
TC-
TC+
TCLK-
TCLK+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLK IN
TC6
GND
N/C
THC63LVDM83R
THC63LVDM63R
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 3 THine Electronics, Inc.
THC63LVDM83R /THC63LVDM63R_Rev2.0
THC63LVDM83R Pin Description
THC63LVDM63R Pin Description
Pin Name
Pin #
Type
Description
TA+, TA-
47, 48
LVDS OUT
LVDS Data Out.
TB+, TB-
45, 46
LVDS OUT
TC+, TC-
41, 42
LVDS OUT
TD+, TD-
37, 38
LVDS OUT
TCLK+, TCLK-
39, 40
LVDS OUT
LVDS Clock Out.
TA0 ~ TA6
51, 52, 54, 55, 56, 3, 4
IN
Pixel Data Inputs.
TB0 ~ TB6
6, 7, 11, 12, 14, 15, 19
IN
TC0 ~ TC6
20, 22, 23, 24, 27, 28, 30
IN
TD0 ~ TD6
50, 2, 8, 10, 16, 18, 25
IN
/PDWN
32
IN
H: Normal operation,
L: Power down (all outputs are Hi-Z)
RS
1
IN
R/F
17
IN
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
VCC
9, 26
Power
Power Supply Pins for TTL inputs and digital
circuitry.
CLKIN
31
IN
Clock in.
GND
5, 13, 21,
29, 53
Ground
Ground Pins for TTL inputs and digital circuitry.
LVDS VCC
44
Power
Power Supply Pins for LVDS Outputs.
LVDS GND
36, 43, 49
Ground
Ground Pins for LVDS Outputs.
PLL VCC
34
Power
Power Supply Pin for PLL circuitry.
PLL GND
33, 35
Ground
Ground Pins for PLL circuitry.
Pin Name
Pin #
Type
Description
TA+, TA-
40, 41
LVDS OUT
LVDS Data Out.
TB+, TB-
38, 39
LVDS OUT
TC+, TC-
34, 35
LVDS OUT
TCLK+, TCLK-
32, 33
LVDS OUT
LVDS Clock Out.
TA0 ~ TA6
44, 45, 47, 48, 1, 3, 4
IN
Pixel Data Inputs.
TB0 ~ TB6
6, 7, 9, 10, 12, 13, 15
IN
TC0 ~ TC6
16, 18, 19, 20, 22, 23, 25
IN
/PDWN
27
IN
H: Normal operation,
L: Power down (all outputs are Hi-Z)
RS
2
IN
LVDS swing control.
RS
LVDS swing
VCC
350mV
:
:
GND
200mV
LVDS swing control.
RS
LVDS swing
VCC
350mV
:
:
GND
200mV
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 4 THine Electronics, Inc.
THC63LVDM83R /THC63LVDM63R_Rev2.0
Absolute Maximum Ratings
1
Electrical Characteristics
CMOS/TTL DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
~ +70
R/F
14
IN
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
VCC
8, 21
Power
Power Supply Pins for TTL inputs and digital
circuitry.
CLKIN
26
IN
Clock in.
GND
5, 11, 17, 24, 46
Ground
Ground Pins for TTL inputs and digital circuitry.
LVDS VCC
37
Power
Power Supply Pins for LVDS Outputs.
LVDS GND
36, 42
Ground
Ground Pins for LVDS Outputs.
PLL VCC
29
Power
Power Supply Pin for PLL circuitry.
PLL GND
28, 30
Ground
Ground Pins for PLL circuitry.
Supply Voltage (V
CC
)
-0.3V ~ +4.0V
CMOS/TTL Input Voltage
-0.3V ~ (V
CC
+ 0.3V)
CMOS/TTL Output Voltage
-0.3V ~ (V
CC
+ 0.3V)
LVDS Driver Output Voltage
-0.3V ~ (V
CC
+ 0.3V)
Output Current
continuous
Junction Temperature
+125
Storage Temperature Range
-55
~ +150
Resistance to soldering heat
+260
/10sec
Maximum Power Dissipation @+25
0.5W
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics"
specify conditions for device operation.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
IH
High Level Input Voltage
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
I
INC
Input Current
A
I
PD
Pull Down Current
R/F pin, VIH=V
CC
100
A
I
RS
RS Pull Down Current
RS pin, VIH=V
CC
100
A
Pin Name
Pin #
Type
Description
C
C
C
C
C
C
C
0V V
IN
V
CC
10
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 5 THine Electronics, Inc.
THC63LVDM83R /THC63LVDM63R_Rev2.0
LVDS Transmitter DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
~ +70
THC63LVDM83R Supply Current
V
CC
= 3.0V ~ 3.6V, Ta = -10
~ +70
.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VOD
Differential Output Voltage
RL=100
Normal
swing
RS=V
CC
250
350
450
mV
Reduced
swing
RS=GND
100
200
300
mV
VOD
Change in VOD between
complementary output states
RL=100
35
mV
VOC
Common Mode Voltage
1.125
1.25
1.375
V
VOC
Change in VOC between
complementary output states
35
mV
I
OS
Output Short Circuit Current
VOUT=0V, RL=100
-24
mA
I
OZ
Output TRI-STATE Current
/PDWN=0V,
V
OUT
=0V to V
CC
A
Symbol
Parameter
Condition(*)
Typ.
Max.
Units
I
TCCG
Transmitter Supply
Current
RL=100
,CL=5pF
V
CC
=3.3V, RS=V
CC
16 Gray Scale Pattern
f=65MHz
36
46
mA
f=85MHz
39
49
mA
RL=100
,CL=5pF
V
CC
=3.3V, RS=GND
16 Gray Scale Pattern
f=65MHz
31
41
mA
f=85MHz
34
44
mA
I
TCCW
Transmitter Supply
Current
RL=100
,CL=5pF
V
CC
=3.3V, RS=V
CC
Worst Cace Pattern
f=65MHz
38
48
mA
f=85MHz
41
51
mA
RL=100
,CL=5pF
V
CC
=3.3V, RS=GND
Worst Cace Pattern
f=65MHz
33
43
mA
f=85MHz
36
46
mA
I
TCCS
Transmitter Power Down
Supply Current
/PDWN = L
10
A
C
C
10
C
C
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