54AC16640, 74AC16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS240A JULY 1990 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The 'AC16640 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the direction-control (1DIR and 2DIR)
inputs. The output-enable (1OE and 2OE) inputs
can be used to disable the device so that the
buses are effectively isolated.
The 74AC16640 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16640 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74AC16640 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each section)
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
54AC16640 . . . WD PACKAGE
74AC16640 . . . DL PACKAGE
(TOP VIEW)
54AC16640, 74AC16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS240A JULY 1990 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
1OE
1A1
47
1B1
2
1B6
9
1B7
11
1B8
12
1B2
3
1B3
5
1B4
6
1B5
8
1
2
2A1
36
2B1
13
2B6
20
2B7
22
2B8
23
2B2
14
2B3
16
2B4
17
2B5
19
4
5
1
1
1
1
G3
48
3 EN2 [AB]
3 EN1 [BA]
1
1DIR
G6
25
6 EN5 [AB]
6 EN4 [BA]
24
2DIR
2OE
logic diagram (positive logic)
1OE
1DIR
1A1
1B1
2
47
1
48
To Seven Other Channels
2OE
2DIR
2A1
2B1
13
36
24
25
To Seven Other Channels
54AC16640, 74AC16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS240A JULY 1990 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
400 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air)(see Note 2): DL package
1.2 W
. . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16640
74AC16640
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
3
5
5.5
V
VCC = 3 V
2.1
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 5.5 V
3.85
3.85
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VCC = 5.5 V
1.65
1.65
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 3 V
4
4
IOH
High-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
VCC = 3 V
12
12
IOL
Low-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
t/
v
Input transition rise or fall rate
0
10
0
10
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16640, 74AC16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS240A JULY 1990 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54AC16640
74AC16640
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
2.48
V
I
24
A
4.5 V
3.94
3.8
3.8
IOH = 24 mA
5.5 V
4.94
4.8
4.8
IOH = 75 mA
5.5 V
3.85
3.85
3 V
0.1
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
0.44
IOL = 24 mA
5.5 V
0.36
0.44
0.44
IOL = 75 mA
5.5 V
1.65
1.65
II
Control inputs
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
80
A
Ci
Control inputs
VI = VCC or GND
5 V
4.5
pF
Cio
A or B ports
VO = VCC or GND
5 V
16
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC16640
74AC16640
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
2.2
6.9
9.1
2.2
10
2.2
10
ns
tPHL
A or B
B or A
3
8.5
11
3
11.9
3
11.9
ns
tPZH
OE
A or B
3
8.2
11
3
12.3
3
12.3
ns
tPZL
OE
A or B
3.9
10.9
14
3.9
15.5
3.9
15.5
ns
tPHZ
OE
A or B
5.1
8.3
10.6
5.1
11.2
5.1
11.2
ns
tPLZ
OE
A or B
4.3
7.8
10.1
4.3
10.6
4.3
10.6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC16640
74AC16640
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
1.8
4.7
1.8
7.3
1.8
7.3
ns
tPHL
A or B
B or A
2.6
5.7
2.6
8.6
2.6
8.6
ns
tPZH
OE
A or B
2.4
5.6
2.4
8
2.4
8
ns
tPZL
OE
A or B
3
6.6
3
9.9
3
9.9
ns
tPHZ
OE
A or B
5
7.5
5
9.9
5
9.9
ns
tPLZ
OE
A or B
4.1
6.5
4.1
9
4.1
9
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16640, 74AC16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS240A JULY 1990 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
55
pF
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF,
f = 1 MHz
8
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveform
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