ChipFind - документация

Электронный компонент: 54ACT11138

Скачать:  PDF   ZIP
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
650-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic
Small-Outline Packages, Plastic Thin
Shrink Small-Outline Packages, Ceramic
Chip Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
The
ACT11138 circuit is designed to be used in
high-performance memory-decoding or data-
routing applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this decoder
and the enable time of the memory are usually less than the typical access time of the memory. This means
that the effective system delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The 54ACT11138 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT11138 is characterized for operation from 40
C to 85
C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
Y0
A
B
C
V
CC
G1
G2A
G2B
(TOP VIEW)
54ACT11138 . . . J PACKAGE
74ACT11138 . . . D, N, OR PW PACKAGE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
G2A
G2B
NC
Y7
Y6
A
Y0
NC
Y1
Y2
54ACT11138 . . . FK PACKAGE
(TOP VIEW)
B
NC
Y5
G1
Y3
GND
NC
NC No internal connection
Y4
C
V
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbols (alternatives)
BIN/OCT
10
G2B
G2A
8
7
6
5
4
3
2
1
0
G1
C
B
A
7
6
5
3
2
1
16
9
11
13
14
15
EN
&
4
2
1
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
&
15
14
13
11
9
16
1
2
3
5
6
7
A
B
C
G1
0
1
2
3
4
5
6
7
8
10
G
7
0
0
DMUX
2
G2B
G2A
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
G1
G2B
G2A
C
B
A
11
9
10
13
14
15
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
8
7
6
5
3
2
1
16
Data
Outputs
Select
Inputs
Enable
Inputs
Pin numbers shown are for the D, J, and N packages.
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
FUNCTION TABLE
ENABLE
SELECT
OUTPUTS
INPUTS
INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
54ACT11138
74ACT11138
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
0
10
ns/ V
TA
Operating free-air temperature
55
125
40
85
C
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT11138
74ACT11138
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.7
3.8
V
VOH
IOH = 24 mA
5.5 V
4.94
4.7
4.8
V
IOH = 50 mA
{
5.5 V
3.85
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
{
5.5 V
1.65
IOL = 75 mA
{
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
m
A
D
ICC
}
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT11138
74ACT11138
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A B C
Any Y
1.5
6.1
8.9
1.5
10.5
1.5
9.8
ns
tPHL
A, B, C
Any Y
1.5
6
8.7
1.5
10.3
1.5
9.7
ns
tPLH
G1
Y
1.5
5.5
8
1.5
9.4
1.5
8.9
ns
tPHL
G1
Y
1.5
6
7.9
1.5
9.5
1.5
8.9
ns
tPLH
G2A G2B
Any Y
1.5
6.4
8.3
1.5
9.9
1.5
9.3
ns
tPHL
G2A, G2B
Any Y
1.5
6
8.8
1.5
10.5
1.5
9.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd Power dissipation capacitance
CL = 50 pF, f = 1 MHz
88
pF
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
Input
(see Note B)
1.5 V
1.5 V
50% VCC
50% VCC
tPHL
tPLH
3 V
Output
VOL
VOH
0 V
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms