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Электронный компонент: 54ACT11470

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54ACT11470, 74ACT11470
8-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configuration
Minimizes High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Ceramic 300-mil DIPs
description
The
ACT11470 is an 8-bit registered bus
transceiver that contains two sets of D-type
flip-flops for temporary storage of data flowing in
either direction. Separate clock (CLKAB or
CLKBA) and output-enable (OEAB or OEBA)
inputs are provided for each register to permit
independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low in
order to enter data from A or to output data to B.
If both CEAB and CLKAB are low, then the B port
presents the level of the A port prior to the most
recent low-to-high transition of CLKAB. Data flow
from B to A is similar, but requires the use of
CEBA, CLKBA, and OEBA inputs.
To avoid false clocking of the flip-flops, CEAB and
CEBA should not be switched from low to high
while CLK is low.
The 54ACT11470 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The 74ACT11470 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
CEAB
CLKAB
OEAB
A
B
H
X
X
X
Z
X
X
H
X
Z
L
L
L
X
B0
L
L
L
L
L
L
H
H
A-to-B data flow is shown: B-to-A flow is similar but
uses CEBA, CLKBA, and OEBA.
Output level before the indicated steady-state input
conditions were established.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CEBA
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
CEAB
OEBA
CLKBA
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKAB
OEAB
54ACT11470 . . . JT PACKAGE
74ACT11470 . . . DW PACKAGE
(TOP VIEW)
GND
GND
GND
A5
A6
A4
B2
B3
B4
GND
B5
B6
3 2 1
13 14
5
6
7
8
9
10
11
B7
B8
CLKAB
OEAB
CEAB
A8
A7
B1
CLKBA
OEBA
CEBA
A1
A2
A3
4
15 16 17 18
54AC11470 . . . FK PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
CC
V
CC
V
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
54ACT11470, 74ACT11470
8-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram (positive logic)
OEBA
CEBA
OEAB
CEAB
A1
2
6D
A2
3
A3
4
A4
5
A5
10
A6
11
A7
12
A8
13
B1
26
5D
B2
25
B3
24
B4
23
B5
20
B6
19
B7
18
B8
17
27
CLKBA
1C5
EN3
28
G1
1
16
CLKAB
2C6
EN4
15
G2
14
3
4
A1
28
2
16
15
14
27
1
26
B1
C1
1D
C1
1D
OEBA
CEBA
OEAB
CEAB
CLKBA
CLKAB
To Seven Other Channels
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
54ACT11470, 74ACT11470
8-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions (see Note 2)
54ACT11470
74ACT11470
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t /
v
Input transition rise or fall rate
0
10
0
10
ns/ V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT11470
74ACT11470
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
5.4
VOH
IOH =
24 mA
4.5 V
3.94
3.7
3.8
V
VOH
IOH = 24 mA
5.5 V
4.94
4.7
4.8
V
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
Control inputs
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
10
5
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
160
80
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
1
mA
Ci
Control inputs
VI = VCC or GND
5 V
4.5
pF
Cio
A or B ports
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT11470, 74ACT11470
8-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
54ACT11470
74ACT11470
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
90
0
90
0
90
MHz
tw
Pulse duration
CLK high or low
5.5
5.5
5.5
ns
t
Setup time
Data before CLK
2
2
2
ns
tsu
Setup time
Data before CEAB
or CEBA
2
2
2
ns
th
Hold time
Data after CLK
3
3
3
ns
th
Hold time
Data after CEAB
or CEBA
3
3
3
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT11470
74ACT11470
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
90
90
90
MHz
tPLH
CLKAB or CLKBA
A or B
3.4
7.3
9
3.4
10.7
3.4
10.1
ns
tPHL
CLKAB or CLKBA
A or B
4.2
8.3
10.2
4.2
12
4.2
11.4
ns
tPZH
OEAB or OEBA
B or A
3
7
9.5
3
11.5
3
10.5
ns
tPZL
OEAB or OEBA
B or A
4.3
8.6
11.4
4.3
15
4.3
13.7
ns
tPHZ
OEAB or OEBA
B or A
4.5
7.9
9.6
4.5
11
4.5
10.5
ns
tPLZ
OEAB or OEBA
B or A
5.1
7.7
9.5
5.1
10.7
5.1
10.2
ns
tPZH
CEAB or CEBA
B or A
3.4
7.3
10
3.4
12
3.4
11.1
ns
tPZL
CEAB or CEBA
B or A
4.6
9
11.9
4.6
15.5
4.6
14.2
ns
tPHZ
CEAB or CEBA
B or A
4.8
7.9
9.9
4.8
11.4
4.8
10.9
ns
tPLZ
CEAB or CEBA
B or A
5.1
7.9
9.8
5.1
11.2
5.1
10.7
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
41
pF
Cpd
Power dissi ation ca acitance er transceiver
Outputs disabled
CL = 50 F, f = 1 MHz
27
F
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT11470, 74ACT11470
8-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms