54ACT11827, 74ACT11827
10-BIT BUFFERS/BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
description
These 10-bit buffers/bus drivers provide high-
performance bus interface for wide data paths or
buses carrying parity.
The 3-state control gate is a 2-input NOR such that
if either G1 or G2 is high, all ten outputs are in the
high-impedance state.
The
ACT11827 provides inverted data.
The 54ACT11827 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The 74ACT11827 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
G1
G2
A
Y
L
L
H
H
L
L
L
L
X
H
X
Z
H
X
X
Z
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
3 2 1
13 14
5
6
7
8
9
10
11
A8
A9
A10
G2
Y10
Y9
Y8
A2
A1
G1
Y1
Y2
Y3
Y4
4
15 16 17 18
GND
GND
GND
GND
Y6
Y7
A3
A4
A5
54ACT11827 . . . FK PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
Y5
A6
A7
54ACT11827 . . . JT PACKAGE
74ACT11827 . . . DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Y1
Y2
Y3
Y4
Y5
GND
GND
GND
GND
Y6
Y7
Y8
Y9
Y10
G1
A1
A2
A3
A4
A5
VCC
VCC
A6
A7
A8
A9
A10
G2
V
CC
V
CC
54ACT11827, 74ACT11827
10-BIT BUFFERS/BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram (positive logic)
G2
G1
&
EN
28
27
A1
26
A2
25
A3
24
A4
Y1
1
Y2
2
Y3
3
Y4
4
15
23
A5
20
A6
19
A7
18
A8
Y5
5
Y6
10
Y7
11
Y8
12
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
17
A9
16
A10
Y9
13
Y10
14
G
1
G
2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
10
11
12
13
14
Y1
28
15
27
26
25
24
23
20
19
18
17
16
5
4
3
2
1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
250 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
}
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
54ACT11827, 74ACT11827
10-BIT BUFFERS/BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions
54ACT11827
74ACT11827
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
0
10
ns/ V
TA
Operating free-air temperature
55
125
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT11827
74ACT11827
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.7
3.8
V
VOH
IOH = 24 mA
5.5 V
4.94
4.7
4.8
V
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.5
10
5
m
A
II
VI = VCC or GND
5.5 V
0.1
1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
160
80
m
A
D
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Co
VO = VCC or GND
5 V
10
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT11827, 74ACT11827
10-BIT BUFFERS/BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT11827
74ACT11827
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A
Y
3.8
6.3
8
3.8
9.9
3.8
9.2
ns
tPHL
A
Y
2.7
6.9
9.5
2.7
11.9
2.7
11.2
ns
tPZH
G
Y
2.6
6.4
9.2
2.6
12.2
2.6
11.3
ns
tPZL
G
Y
3.2
8
11.2
3.2
15.1
3.2
14
ns
tPHZ
G
Y
6.1
8.8
11.1
6.1
12.9
6.1
12
ns
tPLZ
G
Y
5.8
8.3
10.6
5.8
12.4
5.8
11.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance
Outputs enabled
CL = 50 pF
f = 1 MHz
35
pF
Cpd Power dissipation capacitance
Outputs disabled
CL = 50 pF, f = 1 MHz
10
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
[
VCC
3 V
0 V
50% VCC
50% VCC
VOH
VOL
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
Input
(see Note B)
Output
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
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