www.ti.com
PRODUCT PREVIEW
FEATURES
APPLICATIONS
RELATED PRODUCTS
DESCRIPTION
Reference
Timing
CLK
OVR
D[12:0]
CLK
5
DRY
VREF
AIN
AIN
TH1
5
5
DAC2
ADC2
ADC3
DAC1
ADC1
AV
DD
DV
DD
GND
Digital Error Correction
+
-
+
-
B0061-01
DRY
OVR
A1
TH2
A2
A3
TH3
ADS5444
SLWS162 AUGUST 2005
13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER
Industrial Temperature Range = 40
C to 85
C
13-Bit Resolution
250 MSPS Sample Rate
Test and Measurement
SNR = 68.7 dBc at 100-MHz IF and 250 MSPS
Software-Defined Radio
SFDR = 71 dBc at 100-MHz IF and 250 MSPS
Multi-channel Basestation Receivers
SNR = 67.6 dBc at 230-MHz IF and 250 MSPS
Basestation TX Digital Predistortion
SFDR = 78 dBc at 230-MHz IF and 250 MSPS
Communications Instrumentation
2.2 V
PP
Differential Input Voltage
Fully Buffered Analog Inputs
ADS5424 - 14-bit, 105 MSPS
5 V Analog Supply Voltage
ADS5423 - 14-bit, 80 MSPS
3.3 V LVDS Compatible Outputs
ADS5440 - 13-bit, 210 MSPS
Total Power Dissipation: 2.1 W
2's Complement Output Format
TQFP-80 PowerPADTM Package
The ADS5444 is a 13-bit 250 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while
providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5444 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator
is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over
input frequency.
The ADS5444 is available in an 80-pin TQFP PowerPADTM package. The ADS5444 is built on state of the art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial
temperature range (40
C to 85
C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the forma-
Copyright 2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
www.ti.com
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
(1)
ADS5444
SLWS162 AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
(1)
Product
Package-
Package
Specified
Package
Ordering
Transport
Lead
Designator
(1)
Temperature
Marking
Number
Media,
Range
Quantity
ADS5444
HTQFP-80
(2)
PFP
40
C to 85
C
ADS5444I
ADS5444IPFP
Tray, 96
PowerPAD
ADS5444IPFPR
Tape and Reel, 1000
(1)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2)
Thermal pad size: 6 x 6 array of thermal vias with a maximum thermal pad size of 10 mm x 10 mm
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNIT
AV
DD
to GND
6 V
Supply voltage
DRV
DD
to GND
5 V
Analog input to GND
0.3 V to AV
DD
+0.3 V
Clock input to GND
0.3 V to AV
DD
+0.3 V
CLK to CLK
2.5
Digital data output to GND
0.3 V to DRV
DD
+0.3 V
Operating temperature range
40
C to 85
C
Maximum junction temperature
150
C
Storage temperature range
65
C to 150
C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Soldered slug, no airflow
21.7
C/W
Soldered slug, 250-LFPM airflow
15.4
C/W
JA
Unsoldered slug, no airflow
50
C/W
Unsoldered slug, 250-LFPM airflow
43.4
C/W
JC
Bottom of package (heatslug)
2.99
C/W
(1)
Using 36 thermal vias (6 x 6 array). See the Application Section.
2
www.ti.com
PRODUCT PREVIEW
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
ADS5444
SLWS162 AUGUST 2005
MIN
NOM
MAX
UNIT
SUPPLIES
AV
DD
Analog supply voltage
4.75
5
5.25
V
DRV
DD
Output driver supply voltage
3
3.3
3.6
V
ANALOG INPUT
Differential input range
2.2
V
PP
V
CM
Input common mode
2.4
V
CLOCK INPUT
1/t
C
ADCLK input sample rate (sine wave)
250
MSPS
Clock amplitude, differential sine wave
3
Vpp
Clock duty cycle
50%
T
A
Open free air temperature
40
85
C
MIN, TYP, and MAX values at T
A
= 25
C, full temperature range is T
MIN
= 40
C to T
MAX
= 85
C, sampling rate = 250 MSPS,
50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, 1 dBFS differential input, and 3 V
PP
differential clock, unless otherwise
noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
13
Bits
ANALOG INPUTS
Differential input range
2.2
V
pp
Differential input resistance (DC)
1
k
Differential input capacitance
1.5
pF
Analog input bandwidth
1000
MHz
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
2.4
V
DYNAMIC ACCURACY
No missing codes
Tested
DNL
Differential linearity error
f
IN
= 10 MHz
0.9
LSB
INL
Integral linearity error
f
IN
= 10 MHz
1.5
LSB
Offset error
5
5
mV
Offset temperature coefficient
mV/
C
Gain error
5
5
%FS
Gain temperature coefficient
%/
C
PSRR
mV/V
POWER SUPPLY
I
AVDD
Analog supply current
365
mA
I
DRVDD
Output buffer supply current
V
IN
= full scale, f
IN
= 70 MHz, F
S
= 250 MSPS
76
mA
Power dissipation
2.1
W
Power-up time
20
ms
DYNAMIC AC CHARACTERISTICS
f
IN
= 10 MHz
69.1
f
IN
= 70 MHz
68.9
f
IN
= 100 MHz
68.7
SNR
Signal-to-noise ratio
f
IN
= 170 MHz
68.1
dBc
f
IN
= 230 MHz
67.6
f
IN
= 300 MHz
66.8
f
IN
= 400 MHz
66.0
3
www.ti.com
PRODUCT PREVIEW
ADS5444
SLWS162 AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
MIN, TYP, and MAX values at T
A
= 25
C, full temperature range is T
MIN
= 40
C to T
MAX
= 85
C, sampling rate = 250 MSPS,
50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, 1 dBFS differential input, and 3 V
PP
differential clock, unless otherwise
noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
IN
= 10 MHz
83
f
IN
= 70 MHz
77
f
IN
= 100 MHz
71
SFDR
Spurious free dynamic range
f
IN
= 170 MHz
73
dBc
f
IN
= 230 MHz
78
f
IN
= 300 MHz
70
f
IN
= 400 MHz
63
f
IN
= 10 MHz
88
f
IN
= 70 MHz
82
f
IN
= 100 MHz
78
HD2
Second harmonic
f
IN
= 170 MHz
75
dBc
f
IN
= 230 MHz
78
f
IN
= 300 MHz
70
f
IN
= 400 MHz
63
f
IN
= 10 MHz
83
f
IN
= 70 MHz
79
f
IN
= 100 MHz
72
HD3
Third harmonic
f
IN
= 170 MHz
76
dBc
f
IN
= 230 MHz
90
f
IN
= 300 MHz
81
f
IN
= 400 MHz
68
f
IN
= 10 MHz
95
f
IN
= 70 MHz
92
f
IN
= 100 MHz
83
Worst other harmonic/spur (other than
f
IN
= 170 MHz
88
dBc
HD2 and HD3)
f
IN
= 230 MHz
89
f
IN
= 300 MHz
87
f
IN
= 400 MHz
76
f
IN
= 10 MHz
68.8
f
IN
= 70 MHz
68.1
f
IN
= 100 MHz
66.2
SINAD
f
IN
= 170 MHz
66.4
dBc
f
IN
= 230 MHz
67.1
f
IN
= 300 MHz
64.8
f
IN
= 400 MHz
60.2
ENOB
Effective number of bits
f
IN
= 70 MHz
11
Bits
RMS idle channel noise
Inputs tied to common-mode
0.4
LSB
DIGITAL CHARACTERISTICS LVDS DIGITAL OUTPUTS
Differential output voltage
0.35
V
Output offset voltage
1.125
1.375
V
4
www.ti.com
PRODUCT PREVIEW
TIMING CHARACTERISTICS
N
N+1
N+2
N+3
N+4
N
N-1
N-2
N-3
t
A
t
su_c
t
h_c
t
h_D
R
N + 1
N
N + 2
N + 3
N + 4
t
C_DR
t
CLK
t
CLKL
CLK, CLK
D[12:0],
OVR, OVR
DRY, DRY
AIN
t
CLKH
t
DR
t
su_DR
T0073-01
t
r
t
f
TIMING CHARACTERISTICS
ADS5444
SLWS162 AUGUST 2005
Figure 1. Timing Diagram
over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AV
DD
= 5 V, DRV
DD
= 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
A
Aperture delay
ps
t
J
Clock slope independent Aperture uncertainty (jitter)
fs
k
J
Clock slope jitter factor dependency
s/V
Latency
4
cycles
Clock Input
t
CLK
Clock period
4.0
ns
t
CLKH
Clock pulsewidth high
2.0
ns
t
CLKL
Clock pulsewidth low
2.0
ns
Clock to DataReady (DRY)
t
DR
Clock rising to DataReady falling
2.08
ns
t
C_DR
Clock rising to DataReady rising
Clock duty cycle = 50%
(1)
4.08
ns
Clock to DATA, OVR
(2)
t
r
Data V
OL
to Data V
OH
(rise time)
0.8
ns
t
f
Data V
OH
to Data V
OL
(fall time)
0.8
ns
t
su_c
Data valid to clock (setup time)
2.4
ns
t
h_c
Clock to invalid Data (hold time)
5.5
ns
DataReady (DRY)/DATA, OVR
(2)
t
su_DR)
Data valid to DRY
1.7
ns
t
h_DR)
DRY to invalid Data
1.4
ns
(1)
t
C_DR
= t
DR
+ t
CLKH
for clock duty cycles other than 50%
(2)
Data is updated with clock rising edge or DRY falling edge.
5
PDF 
ZIP