Document Outline

• IMPORTANT NOTICE
• REVISION HISTORY
• Contents
• List of Figures
• List of Tables
• 1 SMJ320VC5416 Features
• 2 Introduction
  • 2.1 Description
  • 2.2 Pin Assignments
    • 2.2.1 Pin Assignments for the HFG Package
  • 2.3 Signal Descriptions
• 3 Functional Overview
  • 3.1 Memory
    • 3.1.1 Data Memory
    • 3.1.2 Program Memory
    • 3.1.3 Extended Program Memory
  • 3.2 On-Chip ROM With Bootloader
  • 3.3 On-Chip RAM
  • 3.4 On-Chip Memory Security
  • 3.5 Memory Map
    • 3.5.1 Relocatable Interrupt Vector Table
  • 3.6 On-Chip Peripherals
    • 3.6.1 Software-Programmable Wait-State Generator
    • 3.6.2 Programmable Bank-Switching
    • 3.6.3 Bus Holders
  • 3.7 Parallel I/O Ports
    • 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
    • 3.7.2 HPI Nonmultiplexed Mode
  • 3.8 Multichannel Buffered Serial Ports (McBSPs)
  • 3.9 Hardware Timer
  • 3.10 Clock Generator
  • 3.11 Enhanced External Parallel Interface (XIO2)
  • 3.12 DMA Controller
    • 3.12.1 Features
    • 3.12.2 DMA External Access
    • 3.12.3 DMA Memory Map
    • 3.12.4 DMA Priority Level
    • 3.12.5 DMA Source/Destination Address Modification
    • 3.12.6 DMA in Autoinitialization Mode
    • 3.12.7 DMA Transfer Counting
    • 3.12.8 DMA Transfer in Doubleword Mode
    • 3.12.9 DMA Channel Index Registers
    • 3.12.10 DMA Interrupts
    • 3.12.11 DMA Controller Synchronization Events
  • 3.13 General-Purpose I/O Pins
    • 3.13.1 McBSP Pins as General-Purpose I/O
    • 3.13.2 HPI Data Pins as General-Purpose I/O
  • 3.14 Device ID Register
  • 3.15 Memory-Mapped Registers
  • 3.16 McBSP Control Registers and Subaddresses
  • 3.17 DMA Subbank Addressed Registers
  • 3.18 Interrupts
• 4 Documentation Support
• 5 Electrical Specifications
  • 5.1 Absolute Maximum Ratings
  • 5.2 Recommended Operating Conditions
  • 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted)
  • 5.4 Package Thermal Resistance Characteristics
  • 5.5 Timing Parameter Symbology
  • 5.6 Internal Oscillator With External Crystal
  • 5.7 Clock Options
    • 5.7.1 Divide-By-Two and Divide-By-Four Clock Options
    • 5.7.2 Multiply-By-N Clock Option (PLL Enabled)
  • 5.8 Memory and Parallel I/O Interface Timing
    • 5.8.1 Memory Read
    • 5.8.2 Memory Write
    • 5.8.3 I/O Read
    • 5.8.4 I/O Write
  • 5.9 Ready Timing for Externally Generated Wait States
  • 5.10 HOLD\ and HOLDA\ Timings
  • 5.11 Reset, BIO\, Interrupt, and MP/MC\ Timings
  • 5.12 Instruction Acquisition (IAQ)\ and Interrupt Acknowledge (IACK)\ Timings
  • 5.13 External Flag (XF) and TOUT Timings
  • 5.14 Multichannel Buffered Serial Port (McBSP) Timing
    • 5.14.1 McBSP Transmit and Receive Timings
    • 5.14.2 McBSP General-Purpose I/O Timing
    • 5.14.3 McBSP as SPI Master or Slave Timing
  • 5.15 Host-Port Interface Timing
    • 5.15.1 HPI8 Mode
    • 5.15.2 HPI16 Mode
• 6 Mechanical Data
  • 6.1 Ceramic Quad Flatpack Mechanical Data
    • HFG (S-CQFP-F164) CERAMIC QUAD FLATPACK WITH NCTB