1
Data sheet acquired from Harris Semiconductor
SCHS134E
Features
Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
Asynchronous Reset
Complementary Outputs
Buffered Inputs
Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The 'HC73 and CD74HCT73 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
Pinout
CD54HC73 (CERDIP)
CD74HC73, CD74HCT73 (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC73F3A
-55 to 125
14 Ld CERDIP
CD74HC73E
-55 to 125
14 Ld PDIP
CD74HC73M
-55 to 125
14 Ld SOIC
CD74HC73MT
-55 to 125
14 Ld SOIC
CD74HC73M96
-55 to 125
14 Ld SOIC
CD74HCT73E
-55 to 125
14 Ld PDIP
CD74HCT73M
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
1CP
1R
1K
V
CC
2CP
2R
2J
1J
1Q
1Q
GND
2K
2Q
2Q
1
2
3
4
5
6
7
14
13
12
11
10
9
8
February 1998 - Revised September 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC73, CD74HC73,
CD74HCT73
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
[ /Title
(CD74
HC73,
CD74
HCT73
)
/Sub-
ject
(Dual
J-K
Flip-
Flop
2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUTS
OUTPUTS
R
CP
J
K
Q
Q
L
X
X
X
L
H
H
L
L
No Change
H
H
L
H
L
H
L
H
L
H
H
H
H
Toggle
H
H
X
X
No Change
H =High Level (Steady State)
L
=Low Level (Steady State)
X = Irrelevant
= High-to-Low Transition
2R
12
13
1Q
1Q
6
2
1R
2K
10
5
9
8
2Q
2Q
2CP
FF 1
FF 2
GND = 11
V
CC
= 4
2J
7
1K
3
1
1CP
1J
14
nA
J
K
CL
CL R
12 (9)
Q
13 (8)
Q
14 (7)
3(10)
J
K
1 (5)
CP
2 (6)
R
CD54HC73, CD74HC73, CD74HCT73
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
25mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
86
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54HC73, CD74HC73, CD74HCT73
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
4
-
40
-
80
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
4
-
40
-
80
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.3
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Specifica-
tions table, e.g., 360
A max at 25
o
C.
HC TYPES
HCT TYPES
Input Level
V
CC
3V
V
S
50% V
CC
1.3V
NOTE: Transition times and propagation delay times
Prerequisite For Switching Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
CP Pulse Width
t
w
-C
L
= 50pF
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
R Pulse Width
t
w
-C
L
= 50pF
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
CD54HC73, CD74HC73, CD74HCT73
5
Setup Time, J, K to CP
t
SU
C
L
= 50pF
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Hold Time, J, K to CP
t
H
C
L
= 50pF
2
3
-
-
3
-
3
-
ns
4.5
3
-
-
3
-
3
-
ns
6
3
-
-
3
-
3
-
ns
Removal Time
t
REM
-C
L
= 50pF
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
CP Frequency
f
MAX
C
L
= 50pF
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
25
-
20
-
MHz
C
L
= 15pF
5
-
60
-
-
-
-
-
MHz
C
L
= 50pF
6
35
-
-
29
-
23
-
MHz
HCT TYPES
CP Pulse Width
t
w
C
L
= 50pF
4.5
16
-
-
20
-
24
-
ns
R Pulse Width
t
w
CL = 50pF
4.5
18
-
-
23
-
27
-
ns
Setup Time, J, K to CP
t
SU
CL = 50pF
4.5
16
-
-
20
-
24
-
ns
Hold Time, J, K to CP
t
H
CL = 50pF
4.5
3
-
-
3
-
3
-
ns
Removal Time
t
REM
CL = 50pF
4.5
12
-
-
15
-
18
-
ns
CP Frequency
f
MAX
CL = 50pF
4.5
30
-
-
25
-
20
-
MHz
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
CP to Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
160
-
200
-
240
ns
4.5
-
-
32
-
40
-
48
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
28
-
34
-
41
ns
Propagation Delay,
CP to Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
160
-
200
-
240
ns
4.5
-
-
32
-
40
-
48
ns
C
L
= 15pF
5
-
13
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
28
-
34
-
41
ns
Propagation Delay,
R to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
145
-
180
-
220
ns
4.5
-
-
29
-
36
-
44
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
25
-
31
-
38
ns
Output Transition Time
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Prerequisite For Switching Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC73, CD74HC73, CD74HCT73
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