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1
Data sheet acquired from Harris Semiconductor
SCHS196C
Features
Cascadable
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The 'HC688 and 'HCT688 are 8-bit magnitude comparators
designed for use in computer and logic applications that
require the comparison of two 8-bit binary words. When the
compared words are equal the output (Y) is low and can be
used as the enabling input for the next device in a cascaded
application.
Pinout
CD54HC688, CD54HCT688 (CERDIP)
CD74HC688 (PDIP, SOIC, SOP, TSSOP)
CD74HCT688 (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CD54HC688F3A
-55 to 125
20 Ld CERDIP
CD54HCT688F3A
-55 to 125
20 Ld CERDIP
CD74HC688E
-55 to 125
20 Ld PDIP
CD74HC688M
-55 to 125
20 Ld SOIC
CD74HC688M96
-55 to 125
20 Ld SOIC
CD74HC688NSR
-55 to 125
20 Ld SOP
CD74HC688PWR
-55 to 125
20 Ld TSSOP
CD74HC688PWT
-55 to 125
20 Ld TSSOP
CD74HCT688E
-55 to 125
20 Ld PDIP
CD74HCT688M
-55 to 125
20 Ld SOIC
CD74HCT688M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
E
A0
B0
A1
B1
A2
A3
B2
B3
GND
V
CC
B7
A7
B6
Y
A6
B5
A5
B4
A4
September 1997 - Revised August 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC688, CD74HC688,
CD54HCT688, CD74HCT688
High-Speed CMOS Logic
8-Bit Magnitude Comparator
[ /Title
(CD74
HC688
,
CD74
HCT68
8)
/Sub-
ject
(High
Speed
CMOS
2
Functional Diagram
TRUTH TABLE
INPUTS
OUPUTS
A, B
E
Y
A = B
L
L
A
B
L
H
X
H
H
H = High Voltage Level, L = Low Voltage Level, X = Don't Care
2
4
6
8
13
17
15
11
A0
A7
A6
A5
A4
A3
A2
A1
3
B0
5
B1
7
B2
9
12
14
16
18
B3
B4
B5
B6
19
Y
B7
E
1
CD54HC688, CD74HC688, CD54HCT688, CD74HCT688
3
Logic Diagram
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
1
E
10
20
GND
V
CC
19
Y
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
CD54HC688, CD74HC688, CD54HCT688, CD74HCT688
4
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
NSR (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . .
60
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . .
83
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD54HC688, CD74HC688, CD54HCT688, CD74HCT688
5
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
Enable
0.7
Data Inputs
0.35
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay (Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
170
-
210
-
255
ns
An to Output
4.5
-
-
34
-
42
-
51
ns
C
L
=15pF
5
-
14
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
29
-
36
-
43
ns
Bn to Output
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
170
-
210
-
255
ns
4.5
-
-
34
-
42
-
51
ns
C
L
=15pF
5
-
14
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
29
-
36
-
43
ns
CD54HC688, CD74HC688, CD54HCT688, CD74HCT688