SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C MARCH 1984 REVISED NOVEMBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
These devices contain an 8-input positive-NAND
gate and perform the following Boolean functions
in positive logic:
Y = A
B
C
D
E
F
G
H or
Y = A + B + C + D + E + F + G + H
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP
N
Tube
SN74ALS30AN
SN74ALS30AN
PDIP N
Tube
SN74AS30N
SN74AS30N
Tube
SN74ALS30AD
ALS30A
0
C to 70
C
SOIC
D
Tape and reel
SN74ALS30AD
ALS30A
SOIC D
Tube
SN74AS30D
AS30
Tape and reel
SN74AS30D
AS30
SSOP DB
Tape and reel
SN74AS30DBR
AS30
CDIP
J
Tube
SNJ54ALS30AJ
SNJ54ALS30AJ
55
C to 125
C
CDIP J
Tube
SNJ54AS30J
SNJ54AS30J
55
C to 125
C
LCCC
FK
Tube
SNJ54ALS30AFK
SNJ54ALS30AFK
LCCC FK
Tube
SNJ54AS30FK
SNJ54AS30FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ALS30A, SN54AS30 . . . J PACKAGE
SN74ALS30A, SN74AS30 . . . D OR N PACKAGE
SN74AS30 . . . DB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
C
D
E
F
GND
V
CC
NC
H
G
NC
NC
Y
SN54ALS30A, SN54AS30 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
H
NC
G
NC
NC
C
NC
D
NC
E
B
A
NC
V
NC
CC
NC No internal connection
F
NC
GND
Y
NC
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C MARCH 1984 REVISED NOVEMBER 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
AH
OUTPUT
Y
All inputs H
L
One or more inputs L
H
logic symbol
Y
8
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
logic diagram (positive logic)
Y
8
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
Pin numbers shown are for the D, DB, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C MARCH 1984 REVISED NOVEMBER 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low level input voltage
0.8
V
VIL
Low-level input voltage
0.7
V
IOH
High level output current
'ALS30A
0.4
mA
IOH
High-level output current
'AS30
2
mA
SN54ALS30A
4
IOL
Low-level output current
SN74ALS30A
8
mA
'AS30
20
SN54ALS30A
55
125
TA
Operating free air temperature
SN54AS30
55
125
C
TA
Operating free-air temperature
SN74ALS30A
0
70
C
SN74AS30
0
70
Applies to the 'AS30 and SN74ALS30A across the full operating temperature range, and SN54ALS30A over the temperature range of
55
C to 70
C.
Applies to the SN54ALS30A over the temperature range of 70
C to 125
C.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4 5 V
II = 18 mA
'ALS30A
1.5
V
VIK
VCC = 4.5 V,
II = 18 mA
'AS30
1.2
V
VOH
VCC = 4 5 V to 5 5 V
IOH = 0.4 mA
'ALS30A
VCC2
V
VOH
VCC = 4.5 V to 5.5 V
IOH = 2 mA
'AS30
VCC2
V
IOL = 4 mA
'ALS30A
0.25
0.4
VOL
VCC = 4.5 V
IOL = 8 mA
SN74ALS30A
0.35
0.5
V
IOL = 20 mA
'AS30
0.35
0.5
II
VCC = 5.5 V,
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
A
IIL
VCC = 5 5 V
VI = 0 4 V
'ALS30A
0.1
mA
IIL
VCC = 5.5 V,
VI = 0.4 V
'AS30
0.5
mA
SN54ALS30A
20
112
IO
VCC = 5.5 V,
VO = 2.25 V
SN74ALS30A
30
112
mA
'AS30
30
112
ICCH
VCC = 5 5 V
VI = 0
'ALS30A
0.22
0.36
mA
ICCH
VCC = 5.5 V,
VI = 0
'AS30
0.9
1.5
mA
ICCL
VCC = 5 5 V
VI = 4 5 V
'ALS30A
0.54
0.9
mA
ICCL
VCC = 5.5 V,
VI = 4.5 V
'AS30
3
4.9
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C MARCH 1984 REVISED NOVEMBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
SN54ALS30A
3
15
tPLH
A B C D E F G or H
Y
SN74ALS30A
3
10
ns
tPLH
A, B, C, D, E, F, G, or H
Y
SN54AS30
1
5.5
ns
SN74AS30
1
5
SN54ALS30A
3
15
tPHL
A B C D E F G or H
Y
SN74ALS30A
3
12
ns
tPHL
A, B, C, D, E, F, G, or H
Y
SN54AS30
1
5
ns
SN74AS30
1
4.5
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C MARCH 1984 REVISED NOVEMBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
S1
CL = 50 pF
(see Note A)
7 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
3 V
0 V
0 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
3 V
3 V
0 V
0 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
VOH
VOL
3 V
In-Phase
Output
0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VCC
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
500
500
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
tPHZ
tPZH
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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