CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B APRIL 2003 REVISED APRIL 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 6-V V
CC
Operation (CD54HC646)
D
4.5-V to 5.5-V V
CC
Operation (CD74HCT646)
D
Wide Operating Temperature Range of
55
C to 125
C
D
Balanced Propagation Delays and
Transition Times
D
Standard Outputs Drive Up To 15 LS-TTL
Loads
D
Significant Power Reduction Compared to
LS-TTL Logic ICs
D
Inputs Are TTL-Voltage Compatible
(CD74HCT646)
D
Independent Registers for A and B Buses
D
Multiplexed Real-Time and Stored Data
D
True Data Paths
description/ordering information
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops,
and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can
be performed with these devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and /or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
55
C to 125
C
SOIC M
Tape and reel
CD74HCT646M96
HCT646M
55
C to 125
C
CDIP F
Tube
CD54HC646F3A
CD54HC646F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CD54HC646 . . . F PACKAGE
CD74HCT646 . . . M PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B APRIL 2003 REVISED APRIL 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1 A8
B1 B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
X
X
X
X
X
Unspecified
Input
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B APRIL 2003 REVISED APRIL 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
21
X
3
DIR
X
1
CLKAB
23
CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
X
X
X
X
X
L
H
H or L
X
H
X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OE
OE
Figure 1. Bus-Management Functions
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B APRIL 2003 REVISED APRIL 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
F/F
GND
GND
D
Q
C
C
C
C
P
P
P
P
P
P
B1
N
N
N
N
N
N
GND
To Channels
28
C
C
CLK
VCC
One of Eight Identical Channels
C
VCC
C
OE
DIR
SAB
SBA
CLKAB
CLKBA
A1
24
12
21
3
2
22
1
23
VCC
D
4
20
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B APRIL 2003 REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output drain current per output, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2) M package
46
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for CD54HC646 (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
2
6
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 6 V
4.2
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 6 V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
500
ns
VCC = 6 V
400
TA
Operating free-air temperature
55
125
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions for CD74HCT646 (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
VCC
V
VO
Output voltage
VCC
V
tt
Input transition (rise and fall) time
500
ns
TA
Operating free-air temperature
55
125
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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