SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E OCTOBER 1995 REVISED OCTOBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
4.5-V to 5.5-V V
CC
Operation
D
Inputs Accept Voltages to 5.5 V
D
Max t
pd
of 10 ns at 5 V
D
Inputs Are TTL-Voltage Compatible
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74ACT373N
SN74ACT373N
SOIC
DW
Tube
SN74ACT373DW
ACT373
40
C to 85
C
SOIC DW
Tape and reel
SN74ACT373DWR
ACT373
40
C to 85
C
SOP NS
Tape and reel
SN74ACT373NSR
ACT373
SSOP DB
Tape and reel
SN74ACT373DBR
AD373
TSSOP PW
Tape and reel
SN74ACT373PWR
AD373
CDIP J
Tube
SNJ54ACT373J
SNJ54ACT373J
55
C to 125
C
CFP W
Tube
SNJ54ACT373W
SNJ54ACT373W
LCCC FK
Tube
SNJ54ACT373FK
SNJ54ACT373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54ACT373 . . . J OR W PACKAGE
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D
8Q
4Q
GND
LE
V
CC
SN54ACT373 . . . FK PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E OCTOBER 1995 REVISED OCTOBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1D
1Q
To Seven Other Channels
C1
1D
1
11
3
2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E OCTOBER 1995 REVISED OCTOBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ACT373
SN74ACT373
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t/
v
Input transition rise or fall rate
8
8
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54ACT373
SN74ACT373
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.49
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.49
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.86
3.7
3.76
V
VOH
IOH = 24 mA
5.5 V
4.86
4.7
4.76
V
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.44
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.25
5
2.5
A
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.6
1.5
1.5
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54ACT373
SN74ACT373
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
7
8.5
8
ns
tsu
Setup time, data before LE
7
8.5
8
ns
th
Hold time, data after LE
0
1
1
ns
SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E OCTOBER 1995 REVISED OCTOBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
SN54ACT373
SN74ACT373
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
D
Q
2.5
8.5
10
1.5
12.5
1.5
11.5
ns
tPHL
D
Q
2
8
10
1.5
12.5
1.5
11.5
ns
tPLH
LE
Q
2.5
8.5
11
1.5
12.5
2
11.5
ns
tPHL
LE
Q
2
8
10
1.5
11.5
1.5
11.5
ns
tPZH
OE
Q
2
8
9.5
1.5
11.5
1.5
10.5
ns
tPZL
OE
Q
2
7.5
9
1.5
11
1.5
10.5
ns
tPHZ
OE
Q
2.5
9
11
1.5
14
2.5
12.5
ns
tPLZ
OE
Q
1.5
7.5
8.5
1.5
11
1
10
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
40
pF
SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E OCTOBER 1995 REVISED OCTOBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
VOH
VOL
3 V
0 V
Input
Output
Timing Input
50% VCC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL + 0.3 V
50% VCC
0 V
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
Input
VOH 0.3 V
3 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
VOLTAGE WAVEFORMS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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