1
Data sheet acquired from Harris Semiconductor
SCHS178C
Features
Buffered Inputs
Four Operating Modes: Shift Left, Shift Right, Load
and Store
Can be Cascaded for N-Bit Word Lengths
I/O
0
- I/O
7
Bus Drive Capability and Three-State for
Bus Oriented Applications
Typical f
MAX
= 50MHz at V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
Description
The 'HC259 and 'HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O
0
- I/O
7
) respond only to the low-to-high transition of the clock
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
The three-state input/output I(/O) port has three modes of
operation:
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
S0
OE1
OE2
I/O
6
I/O
4
I/O
2
Q0
I/O
0
MR
GND
V
CC
DS7
Q7
I/O
7
S1
I/O
5
I/O
3
I/O
1
CP
DS0
Ordering Information
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CD54HC299F3A
-55 to 125
20 Ld CERDIP
CD54HCT299F3A
-55 to 125
20 Ld CERDIP
CD74HC299E
-55 to 125
20 Ld PDIP
CD74HC299M
-55 to 125
20 Ld SOIC
CD74HC299M96
-55 to 125
20 Ld SOIC
CD74HCT299E
-55 to 125
20 Ld PDIP
CD74HCT299M
-55 to 125
20 Ld SOIC
CD74HCT299M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
January 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
[ /Title
(CD74
HC299
,
CD74
HCT29
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Uni-
versal
Shift
2
Functional Diagram
MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE
FUNCTION
INPUTS
INPUTS/OUTPUTS
OE1
OE2
S0
S1
Qn (REGISTER)
I/O0 --- I/O7
Read Register
L
L
L
X
L
L
L
L
L
X
H
H
L
L
X
L
L
L
L
L
X
L
H
H
Load Register
X
X
H
H
Qn = I/On
I/On = Inputs
Disable I/O
H
X
X
X
X
(Z)
X
H
X
X
X
(Z)
TRUTH TABLE
FUNCTION
INPUTS
REGISTER OUTPUTS
MR
CP
S0
S1
DS0
DS7
I/On
Q0
Q1
---
Q6
Q7
RESET (CLEAR)
L
X
X
X
X
X
X
L
L
---
L
L
Shift Right
H
h
l
l
X
X
L
q
0
---
q
5
q
6
H
h
l
h
X
X
H
q
0
---
q
5
Q6
Shift Left
H
l
h
X
l
X
q
1
q2
---
q
7
L
H
l
h
X
h
X
q
1
q
2
---
q
7
H
Hold (Do Nothing)
H
l
l
X
X
X
q
0
q
1
---
q
6
q
7
Parallel Load
H
h
h
X
X
l
L
L
---
L
L
H
h
h
X
X
h
H
H
---
H
H
H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage
low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock
transition; X - Voltage level on logic status don't care; Z = Output in high impedance state,
= Low to High Clock Transition.
I/O
THREE-STATE
OUTPUTS
I/O
THREE-STATE
OUTPUTS
SHIFT
REGISTER
MODE SELECTION
CP OE1 OE2
MR
12
2
3
9
20
V
CC
7
6
5
4
8
1
I/O
0
Q0
S0
STANDARD
OUTPUT
I/O
2
I/O
4
I/O
6
BUS LINE
OUTPUTS
GND
10
11
18
DS0
DS7
13
14
15
16
17
19
I/O
1
Q7
S1
STANDARD
OUTPUT
I/O
3
I/O
5
I/O
7
BUS LINE
OUTPUTS
THREE-
STATE
CONTROL
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O,
For -0.5V < V
O
< V
CC
+ 0.5V
For Q Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25mA
For I/O Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
4.5
4.4
-
-
4.4
-
4.4
-
V
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
Qn
I/On
-
-
-
-
-
-
-
-
V
-4
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
Qn
I/On
-
-
-
-
-
-
-
-
V
4
6
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
7.8
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
Three- State Leak-
age Current
V
IL
or V
IH
V
O
= V
CC
or GND
-
6
-
-
0.5
-
5
-
10
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Three- State Leak-
age Current
V
IL
or V
IH
V
O
= V
CC
or GND
-
6
-
-
0.5
-
5
-
10
A
Additional Quies-
cent Device Cur-
rent Per
Input Pin: 1 Unit
Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
S1, MR
0.25
I/O
0
- I/O
7
0.25
DS0, DS7
0.25
S0, CP
0.6
OE1, OE2
0.3
NOTE: Unit Load is
I
CC
limit specific in Static Specifications Table,
e.g., 360
A max. at 25
o
C.
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
5
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
HC TYPES
Maximum Clock
Frequency
f
MAX
2
6
-
-
5
-
-
4
-
-
MHz
4.5
30
-
-
25
-
-
20
-
-
MHz
6
35
-
-
29
-
-
23
-
-
MHz
MR Pulse Width
t
W
2
50
-
-
65
-
-
75
-
-
ns
4.5
10
-
-
13
-
-
15
-
-
ns
6
9
-
-
11
-
-
13
-
-
ns
Clock Pulse Width
t
W
2
80
-
-
100
-
-
120
-
-
ns
4.5
16
-
-
20
-
-
24
-
-
ns
6
14
-
-
17
-
-
20
-
-
ns
Setup Time
DS0, DS7, I/On to Clock
t
SU
2
100
-
-
125
-
-
150
-
-
ns
4.5
20
-
-
25
-
-
30
-
-
ns
6
17
-
-
21
-
-
26
-
-
ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
t
H
2
0
-
-
0
-
-
0
-
-
ns
4.5
0
-
-
0
-
-
0
-
-
ns
6
0
-
-
0
-
-
0
-
-
ns
Recovery Time
MR to Clock
t
REC
2
5
-
-
5
-
-
5
-
-
ns
4.5
5
-
-
5
-
-
5
-
-
ns
6
5
-
-
5
-
-
5
-
-
ns
Setup Time
S1, S0 to Clock
t
SU
2
120
-
-
150
-
-
180
-
-
ns
4.5
24
-
-
30
-
-
36
-
-
ns
6
20
-
-
26
-
-
31
-
-
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
25
-
-
20
-
-
16
-
-
MHz
MR Pulse Width
t
W
4.5
15
-
-
19
-
-
22
-
-
ns
Clock Pulse Width
t
W
4.5
20
-
-
25
-
-
30
-
-
ns
Setup Time DS0, DS7,
I/On, S0, S1 to Clock
t
SU
4.5
20
-
-
25
-
-
30
-
-
ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
t
H
4.5
0
-
-
0
-
-
0
-
-
ns
Recovery Time MR to
Clock
t
REC
4.5
5
-
-
5
-
-
5
-
-
ns
Setup Time S1, S0 to
Clock
t
SU
4.5
27
-
-
34
-
-
41
-
-
ns
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
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