SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F - AUGUST 1995 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 6-V V
CC
Operation
D
Inputs Accept Voltages to 6 V
D
Max t
pd
of 10 ns at 5 V
description/ordering information
The 'AC74 devices are dual positive-edge-
triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube
SN74AC74N
SN74AC74N
SOIC - D
Tube
SN74AC74D
AC74
SOIC - D
Tape and reel
SN74AC74DR
AC74
-40
C to 85
C
SOP - NS
Tape and reel
SN74AC74NSR
AC74
-40 C to 85 C
SSOP - DB
Tape and reel
SN74AC74DBR
AC74
TSSOP - PW
Tube
SN74AC74PW
AC74
TSSOP - PW
Tape and reel
SN74AC74PWR
AC74
CDIP - J
Tube
SNJ54AC74J
SNJ54AC74J
-55
C to 125
C
CFP - W
Tube
SNJ54AC74W
SNJ54AC74W
-55 C to 125 C
LCCC - FK
Tube
SNJ54AC74FK
SNJ54AC74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
SN54AC74 . . . J OR W PACKAGE
SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
NC - No internal connection
CC
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F - AUGUST 1995 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F - AUGUST 1995 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC74
SN74AC74
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
6
2
6
V
VCC = 3 V
2.1
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 5.5 V
3.85
3.85
V
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 5.5 V
1.65
1.65
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 3 V
-12
-12
IOH
High-level output current
VCC = 4.5 V
-24
-24
mA
IOH
High-level output current
VCC = 5.5 V
-24
-24
mA
VCC = 3 V
12
12
IOL
Low-level output current
VCC = 4.5 V
24
24
mA
IOL
Low-level output current
VCC = 5.5 V
24
24
mA
t/
v
Input transition rise or fall rate
8
8
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F - AUGUST 1995 - REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AC74
SN74AC74
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
3 V
2.9
4.49
2.9
2.9
IOH = -50
A
4.5 V
4.4
5.49
4.4
4.4
IOH = -50
A
5.5 V
5.4
5.49
5.4
5.4
VOH
IOH = -12 mA
3 V
2.56
2.4
2.46
V
VOH
IOH = -24 mA
4.5 V
3.86
3.7
3.76
V
IOH = -24 mA
5.5 V
4.86
4.7
4.76
IOH = -50 mA
5.5 V
3.85
IOH = -75 mA
5.5 V
3.85
3 V
0.002
0.1
0.1
0.1
IOL = 50
A
4.5 V
0.001
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.001
0.1
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
IOL = 24 mA
5.5 V
0.36
0.5
0.44
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
Data pins
VI = VCC or GND
5.5 V
0.1
1
1
A
II
Control pins
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
40
20
A
Ci
VI = VCC or GND
5 V
3
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AC74
SN74AC74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
100
70
95
MHz
tw
Pulse duration
PRE or CLR low
5.5
8
7
ns
tw
Pulse duration
CLK
5.5
8
7
ns
tsu
Setup time, data before CLK
Data
4
5
4.5
ns
tsu
Setup time, data before CLK
PRE or CLR inactive
0
0.5
0
ns
th
Hold time, data after CLK
0.5
0.5
0.5
ns
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F - AUGUST 1995 - REVISED OCTOBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
"
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AC74
SN74AC74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
140
95
125
MHz
tw
Pulse duration
PRE or CLR low
4.5
5.5
5
ns
tw
Pulse duration
CLK
4.5
5.5
5
ns
tsu
Setup time, data before CLK
Data
3
4
3
ns
tsu
Setup time, data before CLK
PRE or CLR inactive
0
0.5
0
ns
th
Hold time, data after CLK
0.5
0.5
0.5
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
SN54AC74
SN74AC74
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
100
125
70
95
MHz
tPLH
PRE or CLR
Q or Q
3.5
8
12
1
13
2.5
13
ns
tPHL
PRE or CLR
Q or Q
4
10.5
12
1
14
3.5
13.5
ns
tPLH
CLK
Q or Q
4.5
8
13.5
1
17.5
4
16
ns
tPHL
CLK
Q or Q
3.5
8
14
1
13.5
3.5
14.5
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
"
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
SN54AC74
SN74AC74
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
140
160
95
125
MHz
tPLH
PRE or CLR
Q or Q
2.5
6
9
1
9.5
2
10
ns
tPHL
PRE or CLR
Q or Q
3
8
9.5
1
10.5
2.5
10.5
ns
tPLH
CLK
Q or Q
3.5
6
10
1
12
3
10.5
ns
tPHL
CLK
Q or Q
2.5
6
10
1
10
2.5
10.5
ns
operating characteristics, V
CC
= 3.3 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
45
pF
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