SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A AUGUST 1990 REVISED AUGUST 2001
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D
100-ns Instruction Cycle Time
D
1568 Words of Configurable On-Chip
Data/Program RAM
D
256 Words of On-Chip Program ROM
D
128K Words of Data/Program Space
D
Pin-for-Pin Compatible with the SMJ320C25
D
16 Input and 16 Output Channels
D
16-Bit Parallel Interface
D
Directly Accessible External Data Memory
Space
D
Global Data Memory Interface
D
16-Bit Instruction and Data Words
D
32-Bit ALU and Accumulator
D
Single-Cycle Multiply/Accumulate
Instructions
D
0 to 16-Bit Scaling Shifter
D
Bit Manipulation and Logical Instructions
D
Instruction Set Support for Floating-Point
Operations, Adaptive Filtering, and
Extended-Precision Arithmetic
D
Block Moves for Data/Program
Management
D
Repeat Instructions for Efficient Use of
Program Space
D
Eight Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
D
Serial Port for Direct Codec Interface
D
Synchronization Input for Multiprocessor
Configurations
D
Wait States for Communications to Slow
Off-Chip Memories/Peripherals
D
On-Chip Timer for Control Operations
D
Three External Maskable User Interrupts
D
Input Pin Polled by Software Branch
Instruction
D
Programmable Output Pin for Signalling
External Devices
D
1.6-
m CMOS Technology
D
Single 5-V Supply
D
Packaging:
D
68-Pin Leaded Ceramic Chip Carrier
(FJ Suffix)
D
68-Pin Leadless Ceramic Chip Carrier (FD
Suffix)
D
68-Pin Grid Array Ceramic Package
(GB Suffix)
D
Military Operating Temperature
Range . . . 55
to 125
C
description
The SMJ320C26 Digital Signal Processor is a member of the TMS320 family of VLSI digital signal processors
and peripherals. The TMS320 family supports a wide range of digital signal processing applications, such as
telecommunications, modems, image processing, speech processing, spectrum analysis, audio processing,
digital filtering, high-speed control, graphics, and other computation intensive applications.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
B
3
4
5
6
7
8
9
10
11
1
C
D
E
F
G
A
H
J
K
L
68-PIN GB
PIN GRID ARRAY CERAMIC PACKAGE
(TOP VIEW)
See Pin Assignments Table (Page 2) and Pin
Nomenclature Table (Page 3) for location and
description of all pins.
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A AUGUST 1990 REVISED AUGUST 2001
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description
With a 100-ns instruction cycle time and an
innovative memory configuration, the
SMJ320C26 performs operations necessary for
many real time digital signal processing algo-
rithms. Since most instructions require only one
cycle, the SMJ320C26 is capable of executing ten
million instructions per second. On-chip program-
mable data/program RAM of 1568 words of 16
bits, on-chip program ROM of 256-words, direct
addressing of up to 64K-words of external
program and 64K-words of data memory space,
and multiprocessor interface features for sharing
global memory minimize unnecessary data
transfers to take full advantage of the capabilities
of the processor.
The SMJ320C26 scaling shifter has a 16-bit input
connected to the data bus and a 32-bit output
connected to the ALU. The scaling shifter
produces a left shift of 0 to 16 bits on the input
data, as programmed in the instruction. The LSBs
of the output are filled with zeroes, and the MSBs
may be either filled with zeroes or sign-extended,
depending upon the status programmed into the
SXM (sign-extension mode) bit of status register
ST1.
PGA/LCCC/JLCC PIN ASSIGNMENTS
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
A0
K1/26
A12
K8/40
D2
E1/16
D14
A5/3
INT2
H1/22
VCC
H2/23
A1
K2/28
A13
L9/41
D3
D2/15
D15
B6/2
IS
J11/46
VCC
L6/35
A2
L3/29
A14
K9/42
D4
D1/14
DR
J1/24
MP/MC
A6/1
VSS
B1/10
A3
K3/30
A15
L10/43
D5
C2/13
DS
K10/45
MSC
C10/59
VSS
K11/44
A4
L4/31
BIO
B7/68
D6
C1/12
DX
E11/54
PS
J10/47
VSS
L2/27
A5
K4/32
BR
G11/50
D7
B2/11
FSR
J2/25
READY
B8/66
XF
D11/56
A6
L5/33
CLKOUT1
C11/58
D8
A2/9
FSX
F10/53
RS
A8/65
X1
G10/51
A7
K5/34
CLKOUT2
D10/57
D9
B3/8
HOLD
A7/67
R/W
H11/48
X2/CLKIN
F11/52
A8
K6/36
CLKR
B9/64
D10
A3/7
HOLDA
E10/55
STRB
H10/49
A9
L7/37
CLKX
A9/63
D11
B4/6
IACK
B11/60
SYNC
F2/19
A10
K7/38
D0
F1/18
D12
A4/5
INT0
G1/20
VCC
A10/61
A11
L8/39
D1
E2/17
D13
B5/4
INT1
G2/21
VCC
B10/62
D8
D13
D9
D10
D1
1
D12
D14
V
SS
A1
A2
A3
A4
A5
9 8 7 6 5 4 3
10
11
12
13
14
15
16
D15
RS
MP/MC
BIO
HOLD
READY
CLKR
CLKX
V
CC
V
CC
2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
IACK
MSC
CLKOUT1
CLKOUT2
XF
HOLDA
DX
FSX
A8
A9
A10
A1
1
A12
A13
A14
A15
A6
A7
V
CC
X2/CLKIN
X1
BR
STRB
R/W
PS
IS
DS
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
INT0
INT1
INT2
VCC
DR
FSR
A0
68-PIN FJ AND FD
LEADED AND LEADLESS
CERAMIC CHIP CARRIER PACKAGES
(TOP VIEW)
See Pin Assignments Table (Page 2) and Pin
Nomenclature Table (Page 3) for location and
description of all pins.
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A AUGUST 1990 REVISED AUGUST 2001
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PIN NOMENCLATURE
NAME
I/O/Z
DEFINITION
VCC
I
5-V supply pins.
VSS
I
Ground pins.
X1
O
Output from internal oscillator for crystal.
X2/CLKIN
I
Input to internal oscillator from crystal or external clock.
CLKOUT1
O
Master clock output (crystal or CLKIN frequency/4).
CLKOUT2
O
A second clock output signal.
D15D0
I/O/Z
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces.
A15A0
O/Z
16-bit address bus A15 (MSB) through A0 (LSB).
PS, DS, IS
O/Z
Program, data and I/O space select signals.
R/W
O/Z
Read/write signal.
STRB
O/Z
Strobe signal.
RS
I
Reset input.
INT2, INT1, INT0
I
External user interrupt inputs.
MP/MC
I
Microprocessor/microcomputer mode select pin.
MSC
O
Microstate complete signal.
IACK
O
Interrupt acknowledge signal.
READY
I
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
BR
O
Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space.
XF
O
External flag output (latched software programmable signal).
HOLD
I
Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines
in the high-impedance state.
HOLDA
O
Hold acknowledge signal.
SYNC
I
Synchronization input.
BIO
I
Branch control input. Polled by BIOZ instruction.
DR
I
Serial data receive input.
CLKR
I
Clock input for serial port receiver.
FSR
I
Frame synchronization pulse for receive input.
DX
O/Z
Serial data transmit output.
CLKX
I
Clock input for serial port transmitter.
FSX
I/O/Z
Frame synchronization pulse for transmit. May be configured as either an input or an output.
I/O/Z denotes input/output/high-impedance state.
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A AUGUST 1990 REVISED AUGUST 2001
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional block diagram
RSR(16)
XSR(16)
DRR(16)
DXR(16)
TIM(16)
PRD(16)
IMR(6)
GREG(8)
QIR(16)
IR(16)
ST0(16)
ST1(16)
RPTC(8)
IFR(6)
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
PROGRAM BUS
16
16
16
6
8
16
DR
CLKR
FSR
DX
CLKX
FSX
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
32
32
32
32
32
16
16
16
16
16
16
16
16
16
16
16
7 LSB
FROM
IR
9
16
16
16
16
3
3
3
3
16
16
16
16
3
16
PC(16)
STACK
(8 - 16)
ADDRESS
PROGRAM
ROM
(256 x 16)
INSTRUCTION
PFC(16)
MCS(16)
ARP(3)
ARS(3)
DATA
RAM (32 x 16)
BLOCK B2
DATA/PROG
RAM (512 x 16)
BLOCK B3
DATA/PROG
RAM (512 x 16)
BLOCK B1
DATA/PROG
RAM (512 x 16)
BLOCK B0
SHIFTERS (07)
C
ACCH(16)
ACCL(16)
ALU(32)
SHIFTER (6.0.1.4)
TR(16)
MULTIPLIER
PR(32)
SHIFTER(016)
DP(9)
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
ARAU(16)
MUX
MUX
CONTROLLER
DATA BUS
R/W
STRB
READY
BR
XF
HOLD
HOLDA
MSC
BIO
RS
IACK
MP/MC
INT(2-0)
A15A0
D15D0
PS
DS
IS
SYNC
X1
X2/CLKIN
CLKOUT1
CLKOUT2
PROGRAM BUS
DATA BUS
16
LEGEND:
ACCH
=
Accumulator high
ACCL
=
Accumulator low
ALU
=
Arithmetic logic unit
ARAU
=
Auxiliary register arithmetic unit
ARS
=
Auxiliary register pointer buffer
ARP
=
Auxiliary register pointer
DP
=
Data memory page pointer
DRR
=
Serial port data receive register
DXR
=
Serial port data trademark register
IFR
=
Interrupt flag register
IMR
=
Interrupt mask register
IR
=
Instruction register
MCS
=
Microcall stack
QIR
=
Queue instruction register
PR
=
Product register
PRD
=
Product register for timer
TIM
=
Timer
TR
=
Temporary register
PC
=
Program counter
PFC
=
Prefetch counter
RPTC
=
Repeat instruction counter
GREG
=
Global memory allocation register
RSR
=
Serial port receive shift register
XSR
=
Serial port to transmit shift register
AR0AR7
=
Auxiliary registers
ST0, ST1
=
Status registers
C
=
Carry bit
32
9
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A AUGUST 1990 REVISED AUGUST 2001
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
architecture
The SMJ320C26 architecture is based on the SMJ320C25 with a different internal RAM and ROM configuration.
The SMJ320C26 integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words
of on-chip ROM and 544 words of on-chip RAM for the SMJ320C25. The SMJ320C26 is pin for pin compatible
with the SMJ320C25.
Increased throughput on the SMJ320C26 for many DSP applications is accomplished by means of single cycle
multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic
unit, and faster I/O necessary for data intensive signal processing.
The architectural design of the SMJ320C26 emphasizes overall speed, communication, and flexibility in the
processor configuration. Control signals and instructions provide floating point support, block memory transfers,
communication to slower off-chip devices, and multiprocessing implementations.
Three large on-chip RAM blocks, configurable either as separate program and data spaces or as three
contiguous data blocks, provide increased flexibility in system design. Programs of up to 256 words can be
masked into the internal program ROM. The remainder of the 64K-word program memory space is located
externally. Large programs can execute at full speed from this memory space. Programs can also be
downloaded from slow external memory to high speed on-chip RAM. A data memory address space of 64K
words is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C26
incorporates all of these features as well as many others, including a hardware timer, serial port, and block data
transfer capabilities.
32-bit ALU accumulator
The SMJ320C26 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and
logic instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following
capabilities:
D
Branch to an address specified by the accumulator.
D
Normalize fixed point numbers contained in the accumulator.
D
Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input may be provided from the
Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16-bits on the input data, as specified in the instruction
word. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign
extended, depending upon the value of the SXM (sign extension mode) bit of status register STO.
16
16 bit parallel multiplier
The SMJ320C26 has a 16
16 bit-hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D
A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and
D
A 32-bit Product Register (PR) that holds the product.
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