1
Data sheet acquired from Harris Semiconductor
SCHS141H
Features
Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
Asynchronous Set and Reset
Complementary Outputs
Buffered Inputs
Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HC112, CD54HCT112 (CERDIP)
CD74HC112 (PDIP, SOIC, SOP, TSSOP)
CD74HCT112 (PDIP)
TOP VIEW
Description
The 'HC112 and 'HCT112 utilize silicon-gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.
The HCT logic family is functionally as well as pin-
compatible with the standard LS logic family.
.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1CP
1K
1J
1S
1Q
1Q
GND
2Q
V
CC
2R
2CP
2K
2J
2S
2Q
1R
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC112F3A
-55 to 125
16 Ld CERDIP
CD54HCT112F3A
-55 to 125
16 Ld CERDIP
CD74HC112E
-55 to 125
16 Ld PDIP
CD74HC112MT
-55 to 125
16 Ld SOIC
CD74HC112M96
-55 to 125
16 Ld SOIC
CD74HC112NSR
-55 to 125
16 Ld SOP
CD74HC112PW
-55 to 125
16 Ld TSSOP
CD74HC112PWR
-55 to 125
16 Ld TSSOP
CD74HC112PWT
-55 to 125
16 Ld TSSOP
CD74HCT112E
-55 to 125
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC112, CD74HC112,
CD54HCT112, CD74HCT112
Dual J-K Flip-Flop with Set and Reset
Negative-Edge Trigger
[ /Title
(CD74
HC112
,
CD74
HCT11
2)
/Sub-
ject
(Dual
J-K
Flip-
Flop
with
Set and
Reset
Nega-
March 1998 - Revised October 2003
2
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
S
R
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H (Note 1)
H (Note 1)
H
H
L
L
No Change
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
H
X
X
No Change
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don't Care
= High-to-Low Transition
NOTE:
1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.
1S
2S
2R
4
10
5
6
1Q
1Q
14
15
1R
2K
12
13
9
7
2Q
2Q
2CP
F/F 1
F/F 2
GND = 8
V
CC
= 16
2J
11
1K
2
1
1CP
1J
3
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
25mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time, t
r
, t
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
Package Thermal Impedance,
JA
(see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
4.5
4.4
-
-
4.4
-
4.4
-
V
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
4
-
40
-
80
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
4
-
40
-
80
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 3)
V
CC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
3. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
1S, 2S
0.5
1K, 2K
0.6
1R, 2R
0.65
1J, 2J, 1CP, 2CP
1
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Specifica-
tions table, e.g., 360
A max at 25
o
C.
Prerequisite For Switching Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Pulse Width CP
t
W
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
5
Pulse Width R, S
t
W
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Setup Time J, K, to CP
t
SU
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Hold Time J, K, to CP
t
H
-
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
Removal Time R to CP, S to CP
t
REM
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
CP Frequency
f
MAX
-
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
25
-
20
-
MHz
6
35
-
-
29
-
23
-
MHz
HCT TYPES
Pulse Width CP
t
SU
-
4.5
16
-
-
20
-
24
-
ns
Pulse Width R, S
t
W
-
4.5
18
-
-
23
-
27
-
ns
Setup Time J, K, to CP
t
H
-
4.5
16
-
-
20
-
24
-
ns
Hold Time J, K, to CP
t
REM
-
4.5
3
-
-
3
-
3
-
ns
Removal Time R to CP, S to CP
t
W
-
4.5
20
-
-
25
-
30
-
ns
CP Frequency
f
MAX
-
4.5
30
-
-
25
-
20
-
MHz
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
CP to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
175
-
220
-
265
ns
C
L
= 50pF
4.5
-
-
35
-
44
-
53
ns
C
L
= 15pF
5
-
14
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
30
-
37
-
45
ns
Propagation Delay,
S to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
155
-
195
-
235
ns
C
L
= 50pF
4.5
-
-
31
-
39
-
47
ns
C
L
= 15pF
5
-
13
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
40
ns
Propagation Delay,
R to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
180
-
225
-
270
ns
C
L
= 50pF
4.5
-
-
36
-
45
-
54
ns
C
L
= 15pF
5
-
15
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
31
-
38
-
46
ns
Prerequisite For Switching Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
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