SN54AS885 . . . JT PACKAGE
SN74AS885 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54AS885 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
L/A
P < QIN
P > QIN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
GND
V
CC
PLE
P7
P6
P5
P4
P3
P2
P1
P0
P < QOUT
P > QOUT
NC No internal connection
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
P6
P5
P4
NC
P3
P2
P1
Q7
Q6
Q5
NC
Q4
Q3
Q2
4
26
14 15 16 17 18
Q1
Q0
GND
NC
P
> QOUT
P
< QOUT
P0
P
> QIN
P
< QIN
L/A
NC
PLE
P7
V
C
C
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Latchable P-Input Ports With Power-Up
Clear
Choice of Logical or Arithmetic
(Two's Complement) Comparison
Data and PLE Inputs Utilize pnp Input
Transistors to Reduce dc Loading Effects
Approximately 35% Improvement in
ac Performance Over Schottky TTL While
Performing More Functions
Cascadable to n Bits While Maintaining
High Performance
10% Less Power Than STTL for an 8-Bit
Comparison
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These advanced Schottky devices are capable of
performing high-speed arithmetic or logic
comparisons on two 8-bit binary or two's
complement words. Two fully decoded decisions
about words P and Q are externally available at
two outputs. These devices are fully expandable
to any number of bits without external gates. To
compare words of longer lengths, the P > QOUT
and P < QOUT outputs of a stage handling less
significant bits can be connected to the P > QIN
and P < QIN inputs of the next stage handling
more significant bits. The cascading paths are
implemented with only a two-gate-level delay to
reduce overall comparison times for long words.
Two alternative methods of cascading are shown
in
application information.
The latch is transparent when P latch-enable
(PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry
is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,
P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically
0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74AS885 is characterized for operation from 0
C to 70
C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
COMPARISON
L/A
DATA
P0 P7,
Q0 Q7
P > QIN
P < QIN
P > QOUT
P < QOUT
Logical
H
P > Q
X
X
H
L
Logical
H
P < Q
X
X
L
H
Logical
H
P = Q
H or L
H or L
H or L
H or L
Arithmetic
L
P AG Q
X
X
H
L
Arithmetic
L
Q AG P
X
X
L
H
Arithmetic
L
P = Q
H or L
H or L
H or L
H or L
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
logic symbol
C1
23
PLE
M [ARITH, 2s COMP]
1D
15
P0
16
P1
17
P2
18
P3
>
3
P > QIN
<
2
P < QIN
P > QOUT
13
P > Q
P < QOUT
14
P < Q
19
P4
20
P5
21
P6
22
P7
0
11
Q0
10
Q1
9
Q2
8
Q3
7
Q4
6
Q5
5
Q6
7
4
Q7
M [LOGIC]
1
COMP
1=0 0
7
P
Q
L/A
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
Q0
ARITH
LOGIC
1
2
11
3
10
9
8
7
6
5
4
15
16
17
18
19
20
21
22
23
4MSB =
P0 = Q0
P1 = Q1
P2 = Q2
P3 = Q3
P5 = Q5
P7 = Q7
P6 = Q6
14
13
PLE
P7
P6
P5
P4
P3
P2
P1
P0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
P > QIN
P < QIN
L/A
P < QOUT
P > QOUT
C1
P7
P7
P6
P6
P5
P5
P4
P4
P3
P3
P2
P2
P1
P1
P0
P0
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
1D
Pin numbers shown are for the DW, JT, and NT packages.
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54AS885
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS885
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS885
SN74AS885
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
2
2
mA
IOL
Low-level output current
20
20
mA
tsu*
Setup time, data before PLE
2
2
ns
th*
Hold time, data after PLE
4.5
4
ns
TA
Operating free-air temperature
55
125
0
70
C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS885
SN74AS885
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 2 mA
VCC 2
VCC 2
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.35
0.5
0.35
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
L/A
VCC = 5 5 V
VI = 2 7 V
40
40
A
IIH
Others
VCC = 5.5 V,
VI = 2.7 V
20
20
A
L/A
4
4
IIL
P > QIN, P < QIN
VCC = 5.5 V,
VI = 0.4 V
2
2
mA
P, Q, PLE
1
1
IO
VCC = 5.5 V,
VO = 2.25 V
20
112
20
112
mA
ICC
VCC = 5.5 V,
See Note 1
130
210
130
210
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with all inputs high except L/A, which is low.
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
SN54AS885
SN74AS885
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
L/A
P < QOUT,
2
8.5
14
1
8.5
13
ns
tPHL
L/A
Q
,
P > QOUT
2
7.5
14
1
7.5
13
ns
tPLH
P < QIN,
P < QOUT,
2
5
10
1
5
8
ns
tPHL
,
P > QIN
Q
,
P > QOUT
2
5.5
10
1
5.5
8
ns
tPLH
Any P or Q
P < QOUT,
2
13.5
21
1
13.5
17.5
ns
tPHL
y
data input
Q
,
P > QOUT
2
10
17
1
10
15
ns
All typical values are at VCC = 5 V, TA = 25
C.
APPLICATION INFORMATION
The
AS885 can be cascaded to compare words longer than eight bits. Figure 1 shows the comparison of two 32-bit
words; however, the design is expandable to n bits. Figure 1 shows the optimum cascading arrangement for
comparing words of 32 bits or greater. Typical delay times shown are at V
CC
= 5 V, T
A
= 25
C and use the standard
advanced Schottky load of R
L
= 500
, C
L
= 50 pF.
Figure 2 shows the fastest cascading arrangement for comparing 16-bit or 24-bit words. Typical delay times shown
are at V
CC
= 5 V, T
A
= 25
C and use the standard advanced Schottky load of R
L
= 500
, C
L
= 50 pF.
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PLE
P > QOUT
P < QOUT
H or L
H or L
H or L
H or L
H or L
PLE
13.5 ns
Typical
13.5 ns
Typical
Figure 1. 32-Bit to 72 (n)-Bit Magnitude Comparator
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
H or L
Latch
Enable
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LSP
MSP
MSB
LSB
MSB
24 Bit
24.4 ns
Typical
16 Bit
19 ns
Typical
Figure 2. Fastest Cascading Arrangement for Comparing 16-Bit or 24-Bit Words
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
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