1
Data sheet acquired from Harris Semiconductor
SCHS198C
Features
Maximum Frequency, Typically 60MHz
C
L
= 15pF, V
CC
= 5V, T
A
= 25
o
C
Positive-Edge Clocking
Overriding Reset
Buffered Inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Description
The 'HC4015 consists of two identical, independent, 4-stage
serial-input/parallel-output
registers.
Each
register
has
independent Clock (CP) and Reset (MR) inputs as well as a
single serial Data input. "Q" outputs are available from each
of the four stages on both registers. All register stages are D-
type, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and
shifted over one stage at each positive- going clock
transition. Resetting of all stages is accomplished by a high
level on the reset line.
The device can drive up to 10 low power Schottky equivalent
loads. The 'HC4015 is an enhanced version of equivalent
CMOS types.
Pinout
CD54HC4015
(CERDIP)
CD74HC4015
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CD54HC4015F3A
-55 to 125
16 Ld CERDIP
CD74HC4015E
-55 to 125
16 Ld PDIP
CD74HC4015M
-55 to 125
16 Ld SOIC
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
2CP
2Q
3
1Q
2
1Q
1
1Q
0
1MR
GND
1D
V
CC
2MR
2Q
0
2Q
1
2Q
2
1Q
3
1CP
2D
November 1997 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4015, CD74HC4015
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
[ /Title
(CD74
HC401
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Dual
4-
2
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
CP
D
R
Q
0
Q
1
Q
2
Q
3
l
L
L
q'
0
q'
1
q'
2
h
L
H
q'
0
q'
1
q'
2
X
L
q'
0
q'
1
q'
2
q'
3
X
X
H
L
L
L
L
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don't Care.
= Low to High Clock Transition
= High to Low Clock Transition
q'
n
= Lower case letters indicate the state of the referenced output one set-up time prior to the Low to
High clock transition.
7
6
1MR
1D
1CP
GND = 8
V
CC
= 16
1Q
2
3
10
1Q
3
1Q
1
4
1Q
0
5
9
15
14
2MR
2D
2CP
2Q
2
11
2
2Q
3
2Q
1
12
2Q
0
13
1
CD54HC4015, CD74HC4015
3
t6
f
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD54HC4015, CD74HC4015
4
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Maximum Clock
Frequency
f
MAX
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
Clock Pulse Width
t
W
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
MR Pulse Width
t
W
2
150
-
190
-
225
-
ns
4.5
30
-
38
-
45
-
ns
6
26
-
33
-
38
-
ns
MR Recovery Time
t
REC
2
50
-
65
-
75
-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
Set-up Time,
Data-In to CP
t
SUL,
t
SUH
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
Hold Time,
Data-In to CP
t
H
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Propagation Delay (Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
175
-
220
-
270
ns
Clock to Q
n
4.5
-
-
35
-
44
-
54
ns
C
L
=15pF
5
-
14
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
30
-
37
-
46
ns
MR to Q
n
, (Clock High)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
275
-
345
-
415
ns
4.5
-
-
55
-
64
-
83
ns
C
L
=15pF
25
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
47
-
54
-
71
ns
MR to Q
n
, (Clock Low)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
325
-
400
-
490
ns
4.5
-
-
65
-
81
-
98
ns
C
L
=15pF
25
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
55
-
69
-
83
ns
Output Transition Time
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
IN
C
L
= 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
f
MAX
C
L
=15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation
Capacitance
(Notes 2, 3)
C
PD
C
L
=15pF
5
-
43
-
-
-
-
-
pF
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per shift register.
3. P
D
= V
CC
2
f
i
+
C
L
V
CC
2
where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
CD54HC4015, CD74HC4015
5
Test Circuit and Waveform
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
CD54HC4015, CD74HC4015
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