TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Push-Pull CMOS Output Drives Capacitive
Loads Without Pullup Resistor,
I

8 mA

Very Low Power . . . 100

W Typ at 5 V

Fast Response Time . . . t

PLH

= 2.7

s Typ

With 5-mV Overdrive

Single-Supply Operation . . . 3 V to 16 V

TLC3702M . . . 4 V to 16 V

On-Chip ESD Protection

description

The TLC3702 consists of two independent
micropower voltage comparators designed to
operate from a single supply and be compatible
with modern HCMOS logic systems. They are
functionally similar to the LM339 but use one-
twentieth of the power for similar response times.
The push-pull CMOS output stage drives
capacitive loads directly without a power-
consuming pullup resistor to achieve the stated
response time. Eliminating the pullup resistor not
only reduces power dissipation, but also saves
board space and component cost. The output
stage is also fully compatible with TTL
requirements.

Texas Instruments LinCMOS

process offers

superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS

process offers

extremely stable input offset voltages with large
differential input voltages. This characteristic
makes it possible to build reliable CMOS
comparators.

The TLC3702C is characterized for operation over the commercial temperature range of 0

C to 70

C. The

TLC3702I is characterized for operation over the extended industrial temperature range of 40

C to 85

C. The

TLC3702M is characterized for operation over the full military temperature range of 55

C to 125

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1 20 19

9 10 11 12 13

NC
2OUT
NC
2IN
NC

1IN

1IN +

FK PACKAGE

(TOP VIEW)

1OUT

2IN+

GND

D, JG, OR P PACKAGE

(TOP VIEW)

1OUT

1IN

1IN +
GND

2OUT
2IN
2IN +

NC No internal connection

OUT

symbol (each comparator)

IN +

IN 

LinCMOS is a trademark of Texas Instruments Incorporated.

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

AVAILABLE OPTIONS

VIOmax

PACKAGES

VIOmax

at 25

SMALL OUTLINE

(D)

CERAMIC

(FK)

CERAMIC DIP

(JG)

PLASTIC DIP

(P)

C to 70

5 mV

TLC3702CD

TLC3702CP

C to 85

5 mV

TLC3702ID

TLC3702IP

C to 125

5 mV

TLC3702MD

TLC3702MFK

TLC3702MJG

The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC3702CDR).

functional block diagram (each comparator)

VDD

GND

OUT

Differential

Input

Circuits

IN+

IN

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1)

0.3 V to 18 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, V

(see Note 2)

18 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, I

5 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I

(each output)

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total supply current into V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total current out of GND

40 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TLC3702C

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC3702I 40

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC3702M 55

C to 125

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 60 seconds: FK package

260

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package

260

. . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package

300

. . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN .

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

DISSIPATION RATING TABLE

PACKAGE

POWER RATING

DERATING FACTOR

ABOVE TA = 25

TA = 70

POWER RATING

TA = 85

POWER RATING

TA = 125

POWER RATING

725 mW

5.8 mW/

464 mW

377 mW

145 mW

1375 mW

11.0 mW/

880 mW

715 mW

275 mW

1050 mW

8.4 mW/

672 mW

546 mW

210 mW

1000 mW

8.0 mW/

640 mW

520 mW

N/A

recommended operating conditions

TLC3702C

UNIT

MIN

NOM

MAX

UNIT

Supply voltage, VDD

Common-mode input voltage, VIC

0.2

VDD 1.5

High-level output current, IOH

Low-level output current, IOL

Operating free-air temperature, TA

electrical characteristics at specified operating free-air temperature, V

= 5 V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

TLC3702C

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIO

Input offset voltage

VDD = 5 V to 10 V,
VIC VICRmin

1.2

VIO

Input offset voltage

VIC = VICRmin,
See Note 3

C to 70

6.5

IIO

Input offset current

VIC = 2 5 V

IIO

Input offset current

VIC = 2.5 V

0.3

IIB

Input bias current

VIC = 2 5 V

IIB

Input bias current

VIC = 2.5 V

0.6

VICR

Common mode input voltage range

0 to VDD 1

VICR

Common-mode input voltage range

C to 70

0 to VDD 1.5

CMRR

Common-mode rejection ratio

VIC = VICRmin

kSVR

Supply-voltage rejection ratio

VDD = 5 V to 10 V

VOH

High level output voltage

VID = 1 V,

4.5

4.7

VOH

High-level output voltage

IOH = 4 mA

4.3

VOL

Low level output voltage

VID = 1 V,

210

300

VOL

Low-level output voltage

IOH = 4 mA

375

IDD

Supply current (both comparators)

Outputs low No load

IDD

Supply current (both comparators)

Outputs low, No load

C to 70

All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions

TLC3702I

UNIT

MIN

NOM

MAX

UNIT

Supply voltage, VDD

Common-mode input voltage, VIC

0.2

VDD 1.5

High-level output current, IOH

Low-level output current, IOL

Operating free-air temperature, TA

electrical characteristics at specified operating free-air temperature, V

= 5 V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

TLC3702I

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIO

Input offset voltage

VDD = 5 V to 10 V,

1.2

VIO

Input offset voltage

VIC = VICRmin, See Note 3

C to 85

IIO

Input offset current

VIC = 2 5 V

IIO

Input offset current

VIC = 2.5 V

IIB

Input bias current

VIC = 2 5 V

IIB

Input bias current

VIC = 2.5 V

VICR

Common mode input voltage range

0 to

VDD 1

VICR

Common-mode input voltage range

C to 85

0 to

VDD 1.5

CMRR

Common-mode rejection ratio

VIC = VICRmin

kSVR

Supply-voltage rejection ratio

VDD = 5 V to 10 V

VOH

High level output voltage

VID = 1 V

IOH = 4 mA

4.5

4.7

VOH

High-level output voltage

VID = 1 V,

IOH = 4 mA

4.3

VOL

Low level output voltage

VID = 1 V

IOH = 4 mA

210

300

VOL

Low-level output voltage

VID = 1 V,

IOH = 4 mA

400

IDD

Supply current (both comparators)

Outputs low

No load

IDD

Supply current (both comparators)

Outputs low,

No load

C to 85

All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions

TLC3702M

UNIT

MIN

NOM

MAX

UNIT

Supply voltage, VDD

Common-mode input voltage, VIC

VDD 1.5

High-level output current, IOH

Low-level output current, IOL

Operating free-air temperature, TA

125

electrical characteristics at specified operating free-air temperature, V

= 5 V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

TLC3702M

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIO

Input offset voltage

VDD = 5 V to 10 V,

1.2

VIO

Input offset voltage

VIC = VICRmin, See Note 3

C to 125

IIO

Input offset current

VIC = 2 5 V

IIO

Input offset current

VIC = 2.5 V

125

IIB

Input bias current

VIC = 2 5 V

IIB

Input bias current

VIC = 2.5 V

125

VICR

Common mode input voltage range

0 to

VDD 1

VICR

Common-mode input voltage range

C to 125

0 to

VDD 1.5

CMRR

Common-mode rejection ratio

VIC = VICRmin

125

kSVR

Supply-voltage rejection ratio

VDD = 5 V to 10 V

125

VOH

High level output voltage

VID = 1 V

IOH = 4 mA

4.5

4.7

VOH

High-level output voltage

VID = 1 V,

IOH = 4 mA

125

4.2

VOL

Low level output voltage

VID = 1 V

IOH = 4 mA

210

300

VOL

Low-level output voltage

VID = 1 V,

IOH = 4 mA

125

500

IDD

Supply current (both comparators)

Outputs low

No load

IDD

Supply current (both comparators)

Outputs low,

No load

C to 125

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

switching characteristics, V

= 5 V, T

= 25

PARAMETER

TEST CONDITIONS

TLC3702C, TLC3702I

TLC3702M

UNIT

MIN

TYP

MAX

Overdrive = 2 mV

4.5

10 kH

Overdrive = 5 mV

2.7

tPLH

Propagation delay time, low-to-high-level output

f = 10 kHz,
CL = 50 pF

Overdrive = 10 mV

1.9

CL = 50 F

Overdrive = 20 mV

1.4

Overdrive = 40 mV

1.1

VI = 1.4 V step at IN+

1.1

Overdrive = 2 mV

10 kH

Overdrive = 5 mV

2.3

tPHL

Propagation delay time, high-to-low-level output

f = 10 kHz,
CL = 50 pF

Overdrive = 10 mV

1.5

CL = 50 F

Overdrive = 20 mV

0.95

Overdrive = 40 mV

0.65

VI = 1.4 V step at IN+

0.15

Fall time

f = 10 kHz,
CL = 50 pF

Overdrive = 50 mV

Rise time

f = 10 kHz,
CL = 50 pF

Overdrive = 50 mV

125

Simultaneous switching of inputs causes degradation in output response.

LinCMOS and Advanced LinCMOS are trademarks of Texas Instruments Incorporated.

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

LinCMOS

process

The LinCMOS

process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply

applications, LinCMOS

products facilitate the design of a wide range of high-performance analog functions

from operational amplifiers to complex mixed-mode converters.

While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS

products. Further questions should be directed to the nearest TI field sales office.

electrostatic discharge

CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being
used and the unused pins are left open, high voltages tend to develop. If there is no provision for ESD protection,
these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage
buildup, each pin is protected by internal circuitry.

Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.

To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI
ESD-protection circuit is presented on the next page.

All input and output pins on LinCMOS

and Advanced LinCMOS

products have associated ESD-protection

circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through
a 1500-

resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor

(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.

To Protect Circuit

Input

GND

VDD

Figure 1. LinCMOS

ESD-Protection Schematic

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

input protection circuit operation

Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.

positive ESD transients

Initial positive charged energy is shunted through Q1 to V

. Q1 turns on when the voltage at the input rises

above the voltage on the V

pin by a value equal to the V

of Q1. The base current increases through R2

with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (V

22 to 26 V) and turn Q2 on. The shunted input current through Q1 to V

now shunted through the n-channel enhancement-type MOSFET Q2 to V

. If the voltage on the input pin

continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate-oxide voltage of the circuit to be protected.

negative ESD transients

The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is 0.3 V to 1 V (the forward
voltage of D1 and D2).

circuit-design considerations

LinCMOS

products are being used in actual circuit environments that have input voltages that exceed the

recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V

ICR

and not damage the device

only if the inputs are current limited. The recommended current limit shown on most product data sheets is

5 mA. Figure 2 and Figure 3 show typical characteristics for input voltage versus input current.

Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the V

pin and into the device I

or the V

supply through R2

producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input
voltage is below the V

of Q2.

When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 4).

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

circuit-design considerations (continued)

Figure 2

VDD

VDD + 4

VDD + 8

VDD + 12

INPUT CURRENT

INPUT VOLTAGE

TA = 25

VI Input Voltage V

Input Current mA
I I

Figure 3

VDD 0.3

VI Input Voltage V

INPUT CURRENT

INPUT VOLTAGE

TA = 25

VDD 0.5

VDD 0.7

VDD 0.9

Input Current mA
I I

1/2

TLC3702

Vref

VDD

See Note A

NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required.

Negative Voltage Input Current Limit :

(

0.3 V)

5 mA

0.3 V

5 mA

Positive Voltage Input Current Limit :

Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS

Comparator

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

The TLC3702 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo
loop which is designed to force the device output to a level within this linear region. Since the servo-loop method
of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset
voltage, common-mode rejection, etc.

To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high.
With the input polarity reversed, the output should be low.

A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed to provide greater accuracy, as shown in Figure 5(b) for the V

ICR

test. This slewing is done instead

of changing the input voltages.

A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.

Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates
a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any
residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed
by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a
duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when
the voltage at the noninverting input exactly equals the input offset voltage.

Voltage dividers R8 and R9 provide an increase in input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it
is suggested that their tolerance level be one percent or lower.

Measuring the extremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board
leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.

5 V

Applied VIO

Limit

1 V

Applied VIO

Limit

 4 V

(a) VIO WITH VIC = 0 V

(b) VIO WITH VIC = 4 V

Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

DUT

VDD

47 k

1.8 k

0.68

IC1c

1/4 TLC274CN

IC1a

1/4 TLC274CN

IC1b

1/4 TLC274CN

1 M

1.8 k

10 k

240 k

10 k

0.1

R3
100

C4
0.1

Integrator

R9
100

Buffer

Triangle
Generator

VIO
(X100)

Figure 6. Circuit for Input Offset Voltage Measurement

Response time is defined as the interval between the application of an input step function and the instant when
the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from
the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the
trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected
by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as
shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV
overdrive, causes the output to change state.

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

VIO

Input offset voltage

Distribution

IIB

Input bias current

vs Free-air temperature

CMRR

Common-mode rejection ratio

vs Free-air temperature

kSVR

Supply-voltage rejection ratio

vs Free-air temperature

VOH

High level output current

vs Free-air temperature

VOH

High-level output current

vs High-level output current

VOL

Low level output voltage

vs Low-level output current

VOL

Low-level output voltage

vs Free-air temperature

Transition time

vs Load capacitance

Supply current response

vs Time

Low-to-high-level output response

Low-to-high level output propagation delay time

High-to-low level output response

High-to-low level output propagation delay time

tPLH

Low-to-high level output propagation delay time

vs Supply voltage

tPHL

High-to-low level output propagation delay time

vs Supply voltage

vs Frequency

IDD

Supply current

vs Supply voltage

vs Free-air temperature

Figure 8

ÇÇ

ÉÉ

ÇÇ

ÉÉ

ÇÇ

Number of Units

VDD = 5 V

VIC = 2.5 V

TA = 25

 5

 4

 3

 2

 1

VIO Input Offset Voltage mV

DISTRIBUTION OF INPUT

OFFSET VOLTAGE

200

180

160

140

120

100

698 Units Tested
From 4 Wafer Lots

Figure 9

TA Free-Air Temperature 

 Input Bias Current nA

100

125

0.1

0.01

0.001

INPUT BIAS CURRENT

FREE-AIR TEMPERATURE

VDD = 5 V

VIC = 2.5 V

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

CMRR Common-Mode Rejection Ratio dB

TA Free-Air Temperature 

COMMON-MODE REJECTION RATIO

FREE-AIR TEMPERATURE

 75

 50

 25

100

125

VDD = 5 V

Figure 11

 75

 50

 25

100

125

SVR

 Supply V

oltage Rejection Ratio dB

TA Free-Air Temperature 

SUPPLY VOLTAGE REJECTION RATIO

FREE-AIR TEMPERATURE

VDD = 5 V to 10 V

Figure 12

TA Free-Air Temperature 

HIGH-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

OH High-Level Outout V

oltage V

VDD = 5 V

IOH = 4 mA

 75

 50

 25

100

125

4.9

4.8

4.7

4.6

4.5

4.55

4.65

4.75

4.85

4.95

Figure 13

VDD = 16 V

IOH High-Level Output Current mA

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

TA = 25

3 V

4 V

5 V

10 V

 2.5

 5

 7.5

 10 12.5

 15 17.5 20

 High-Input Level Output V

oltage

VDD

 0.25

 0.5

 0.75

 1

 1.25

 1.5

 1.75

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 14

IOL Low-Level Output Current mA

 Low-Level Output V

oltage V

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

3 V

4 V

10 V

VDD = 16 V

5 V

1.5

1.25

0.75

0.5

0.25

TA = 25

Figure 15

 75

 50

 25

100

125

TA Free-Air Temperature 

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

 Low-Level Output V

oltage mV

400

350

300

250

200

150

100

VDD = 5 V
IOL = 4 mA

Figure 16

200

400

600

800

1000

CL Load Capacitance pF

t T

ransition

ime

OUTPUT TRANSITION TIME

LOAD CAPACITANCE

250

225

200

175

150

125

100

VDD = 5 V
TA = 25

Rise Time

Fall Time

Figure 17

I DD

 Supply

SUPPLY CURRENT RESPONSE

TO AN OUTPUT VOLTAGE TRANSITION

Current mA

t Time

Output

oltage V

VDD = 5 V
CL = 50 pF
f = 10 kHz

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

 Output

oltage V

Input

oltage mV

Differential

LOW-TO-HIGH-LEVEL OUTPUT RESPONSE

FOR VARIOUS INPUT OVERDRIVES

tPLH Low-to-High-Level Output

Response Time 

VDD = 5 V
TA = 25

CL = 50 pF

100

40 mV
20 mV
10 mV

5 mV
2 mV

Figure 19

40 mV
20 mV
10 mV

5 mV
2 mV

HIGH-TO-LOW-LEVEL OUTPUT RESPONSE

FOR VARIOUS INPUT OVERDRIVES

tPHL High-to-Low-Level Output

Response Time 

 Output

oltage V

Input

oltage mV

Differential

100

VDD = 5 V
TA = 25

CL = 50 pF

Figure 20

LOW-TO-HIGH-LEVEL

OUTPUT RESPONSE TIME

SUPPLY VOLTAGE

Overdrive = 2 mV

5 mV

10 mV

20 mV

40 mV

VDD Supply Voltage V

CL = 50 pF
TA = 25

PLH

Low-to-High-Level

Output Response 

Figure 21

HIGH-TO-LOW-LEVEL

OUTPUT RESPONSE TIME

SUPPLY VOLTAGE

5 mV

10 mV

20 mV

40 mV

CL = 50 pF
TA = 25

VDD Supply Voltage V

t PHL

 High-to-Low-Level

Output Response 

Overdrive = 2 mV

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 22

AVERAGE SUPPLY CURRENT

(PER COMPARATOR)

FREQUENCY

10000

1000

100

 Supply Current 

0.01

0.1

100

f Frequency kHz

VDD = 16 V

5 V

4 V

10 V

3 V

TA = 25

CL = 50 pF

Figure 23

SUPPLY CURRENT

SUPPLY VOLTAGE

VDD Supply Voltage V

Outputs Low
No Loads

 Supply Current 

TA = 25

TA = 125

TA = 40

TA = 55

TA = 85

SUPPLY CURRENT

FREE-AIR TEMPERATURE

 75

 50

 25

100

125

TA Free-Air Temperature 

I DD

 Supply Current 

Outputs High

Outputs Low

VDD = 5 V
No Load

Figure 24

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the
electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged
as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain
within the common-mode range. For example, at 25

C with V

= 5 V, both inputs must remain between

0.2 V and 4 V to ensure proper device operation.

To ensure reliable operation, the supply should be decoupled with a capacitor (0.1

F) that is positioned as close

to the device as possible.

The TLC3702 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as
tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as
exposure to ESD may result in the degradation of the device parametric performance.

Table of Applications

FIGURE

Pulse-width-modulated motor speed controller

Enhanced supply supervisor

Two-phase nonoverlapping clock generator

Micropower switching regulator

C1
0.01

(see Note B)

5 V

1/2 TLC3702

Motor Speed Control
Potentiometer

10 k

100 k

10 k

See
Note A

1/2 TLC3704

10 k

5 V

DIR

SN75603

Half-H Driver

12 V

Motor

DIR

12 V

Direction

Control

S1
SPDT

5 V

SN75604

Half-H Driver

NOTES: A. The recommended minimum capacitance is 10

F to eliminate common ground switching noise.

B. Adjust C1 for change in oscillator frequency.

Figure 25. Pulse-Width-Modulated Motor Speed Controller

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

1/2 TLC3702

P Interrupt

Early Power Fail

1 k

3.3 k

(see Note B)

1/2 TLC3702

10 k

5 V

12-V

Sense

V(UNREG)

(see Note A)

12 V

RESIN

REF

GND

RESET

SENSE

VCC

Reset

Monitors 5 VDC Rail
Monitors 12 VDC Rail
Early Power Fail Warning

TL7705A

2.5 V

NOTES: A.

(UNREG)

2.5

(R1 +R2)

B. The value of CT determines the time delay of reset.

Figure 26. Enhanced Supply Supervisor

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

100 k

C1
180

(see Note A)

1/2 TLC3702

Tantalum

100 k

1/2 TLC3702

TLC271
(see Note B)

270 k

100 k

100 pF

100 k

IN5818

R = 6

L = 1 mH
(see Note D)

470

SK9504

(see Note C)

6 V to 16 V

0.01 mA to 0.25 mA

2.5

(R1

)

R2)

LM385
2.5 V

NOTES: A. Adjust C1 for a change in oscillator frequency

B. TLC271 Tie pin 8 to pin 7 for low bias operation

C. SK9504 VDS = 40 V

IDS = 1 A

D. To achieve microampere current drive, the inductance of the circuit must be increased.

Figure 28. Micropower Switching Regulator

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047 / D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

0.014 (0,35)

0.020 (0,51)

0.157 (4,00)

0.150 (3,81)

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

(8,55)

(8,75)

0.337

0.344

(9,80)

0.394

(10,00)

0.386

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

 8

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TLC3702

DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

4040140 / D 10/96

28 TERMINAL SHOWN

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

NO. OF

MIN

MAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)

(18,78)

0.020 (0,51)

TERMINALS

0.080 (2,03)
0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.035 (0,89)

0.010 (0,25)

0.020 (0,51)
0.010 (0,25)

B SQ

A SQ

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)
0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.

E. Falls within JEDEC MS-004

TLC3702
DUAL MICROPOWER LinCMOS

VOLTAGE COMPARATORS

SLCS013D NOVEMBER 1986 REVISED NOVEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE PACKAGE

0.310 (7,87)
0.290 (7,37)

0.014 (0,36)
0.008 (0,20)

Seating Plane

4040107/C 08/96

0.065 (1,65)
0.045 (1,14)

0.020 (0,51) MIN

0.400 (10,20)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)
0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

15

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

E. Falls within MIL-STD-1835 GDIP1-T8

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER'S RISK.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.

1998, Texas Instruments Incorporated

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