TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Very Low Dropout Voltage, Less Than 0.6 V
at 150 mA
D
Very Low Quiescent Current
D
TTL- and CMOS-Compatible Enable on
TL751L Series
D
60-V Load-Dump Protection
D
Reverse Transient Protection Down To
-50 V
D
Internal Thermal-Overload Protection
D
Overvoltage Protection
D
Internal Overcurrent-Limiting Circuitry
D
Less Than 500-
A Disable (TL751L Series)
description/ordering information
The TL750L and TL751L series of fixed-output voltage regulators offer 5-V, 8-V, 10-V, and 12-V options. The
TL751L series also has an enable (ENABLE) input. When ENABLE is high, the regulator output is placed in the
high-impedance state. This gives the designer complete control over power up, power down, or emergency
shutdown.
The TL750L and TL751L series are low-dropout positive-voltage regulators specifically designed for
battery-powered systems. These devices incorporate overvoltage and current-limiting protection circuitry,
along with internal reverse-battery protection circuitry to protect the devices and the regulated system. The
series is fully protected against 60-V load-dump and reverse-battery conditions. Extremely low quiescent
current during full-load conditions makes these devices ideal for standby power systems.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUT
NC
NC
NC
INPUT
NC
COMMON
NC
8
7
6
5
OUTPUT
COMMON
COMMON
NC
INPUT
COMMON
COMMON
NC
TL750L . . . D PACKAGE
(TOP VIEW)
TL750L . . . KC PACKAGE
(TOP VIEW)
TL750L . . . LP PACKAGE
(TO-92, TO-226AA)
(TOP VIEW)
OUTPUT
COMMON
COMMON
NC
INPUT
COMMON
COMMON
ENABLE
OUTPUT
NC
NC
NC
INPUT
NC
COMMON
ENABLE
TL750L . . . P PACKAGE
(TOP VIEW)
TL751L . . . D PACKAGE
(TOP VIEW)
TL751L . . . P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
INPUT
COMMON
OUTPUT
NC - No internal connection
TL750L . . . KTE PACKAGE
(TOP VIEW)
OUTPUT
COMMON
INPUT
COMMON
COMMON
OUTPUT
INPUT
COMMON
NC - No internal connection
NC - No internal connection
NC - No internal connection
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TJ
VO TYP
AT 25
C
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
POWER-FLEX (KTE)
Reel of 2000
TL750L05CKTER
TL750L05C
Tube of 75
TL750L05CD
50L05C
SOIC (D)
Reel of 2500
TL750L05CDR
50L05C
5 V
SOIC (D)
Tube of 75
TL751L05CD
51L05C
5 V
Reel of 2500
TL751L05CDR
51L05C
TO-226 / TO-92 (LP)
Bulk of 1000
TL750L05CLP
750L05C
TO-226 / TO-92 (LP)
Reel of 2000
TL750L05CLPR
750L05C
TO-220 (KC)
Tube of 50
TL750L05CKC
TL750L05C
SOIC (D)
Tube of 75
TL750L08CD
50L08C
8 V
SOIC (D)
Reel of 2500
TL750L08CDR
50L08C
8 V
TO-226 / TO-92 (LP)
Bulk of 1000
TL750L08CLP
750L08C
0
C to 125
C
PDIP (P)
Tube of 50
TL751L10CP
TL751L10C
0 C to 125 C
Tube of 75
TL750L10CD
50L10C
SOIC (D)
Reel of 2500
TL750L10CDR
50L10C
10 V
SOIC (D)
Tube of 75
TL751L10CD
51L10C
10 V
Reel of 2500
TL751L10CDR
51L10C
TO-226 / TO-92 (LP)
Bulk of 1000
TL750L10CLP
750L10C
TO-226 / TO-92 (LP)
Reel of 2000
TL750L10CLPR
750L10C
Tube of 75
TL750L12CD
50L12C
SOIC (D)
Reel of 2500
TL750L12CDR
50L12C
12 V
SOIC (D)
Tube of 75
TL751L12CD
51L12C
12 V
Reel of 2500
TL751L12CDR
51L12C
TO-226 / TO-92 (LP)
Bulk of 1000
TL750L12CLP
750L12C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DEVICE
COMPONENT
COUNT
Transistors
20
JFETs
2
Diodes
5
Resistors
16
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating junction temperature range (unless otherwise noted)
Continuous input voltage
26 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient input voltage, T
A
= 25
C (see Note 1)
60 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous reverse input voltage -15
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient reverse input voltage, t
100 ms
-50 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, T
J
150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The transient input voltage rating applies to the waveform shown in Figure 1.
package thermal data (see Note 2)
PACKAGE
BOARD
JC
JA
PDIP (P)
High K, JESD 51-7
57
C/W
85
C/W
POWER-FLEX (KTE)
High K, JESD 51-5
3
C/W
23
C/W
SOIC (D)
High K, JESD 51-7
39
C/W
97
C/W
TO-226 / TO-92 (LP)
High K, JESD 51-7
55
C/W
140
C/W
TO-220 (KC)
High K, JESD 51-5
3
C/W
19
C/W
NOTE 2: Maximum power dissipation is a function of TJ(max),
JA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/
JA. Operating at the absolute maximum TJ of 150
C can affect reliability.
recommended operating conditions over recommended operating junction temperature range
(unless otherwise noted)
MIN
MAX
UNITS
TL75xL05
6
26
VI
Input voltage
TL75xL08
9
26
V
VI
Input voltage
TL75xL10
11
26
V
TL75xL12
13
26
VIH
High-level ENABLE input voltage
TL751Lxx
2
15
V
VIL
Low-level ENABLE input voltage
TJ = 25
C
TL751Lxx
-0.3
0.8
V
VIL
Low-level ENABLE input voltage
TJ = 0
C to 125
C
TL751Lxx
-0.15
0.8
V
IO
Output current range
TL75xLxx
0
150
mA
TJ
Operating virtual junction temperature
TL75xLxxC
0
125
C
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for ENABLE voltage
levels and temperature only.
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, V
I
= 14 V, I
O
= 10 mA, T
J
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TL750L05
TL751L05
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
VI = 6 V to 26 V,
IO = 0 to 150 mA
TJ = 25
C
4.80
5
5.2
V
Output voltage
VI = 6 V to 26 V,
IO = 0 to 150 mA
TJ = 0
C to 125
C
4.75
5.25
V
Input regulation voltage
VI = 9 V to 16 V
5
10
mV
Input regulation voltage
VI = 6 V to 26 V
6
30
mV
Ripple rejection
VI = 8 V to 18 V,
f = 120 Hz
60
65
dB
Output regulation voltage
IO = 5 mA to 150 mA
20
50
mV
Dropout voltage
IO = 10 mA
0.2
V
Dropout voltage
IO = 150 mA
0.6
V
Output noise voltage
f = 10 Hz to 100 kHz
500
V
IO = 150 mA
10
12
Input bias current
VI = 6 V to 26 V,
IO = 10 mA,
TJ = 0
C to 125
C
1
2
mA
Input bias current
ENABLE > 2 V
0.5
mA
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a 0.1-
F capacitor across the input and a 10-
F capacitor, with equivalent
series resistance of less than 0.4
, across the output.
electrical characteristics, V
I
= 14 V, I
O
= 10 mA, T
J
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TL750L08
TL751L08
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
VI = 9 V to 26 V,
IO = 0 to 150 mA
TJ = 25
C
7.68
8
8.32
V
Output voltage
VI = 9 V to 26 V,
IO = 0 to 150 mA
TJ = 0
C to 125
C
7.6
8.4
V
Input regulation voltage
VI = 10 V to 17 V
10
20
mV
Input regulation voltage
VI = 9 V to 26 V
25
50
mV
Ripple rejection
VI = 11 V to 21 V,
f = 120 Hz
60
65
dB
Output regulation voltage
IO = 5 mA to 150 mA
40
80
mV
Dropout voltage
IO = 10 mA
0.2
V
Dropout voltage
IO = 150 mA
0.6
V
Output noise voltage
f = 10 Hz to 100 kHz
500
V
IO = 150 mA
10
12
Input bias current
VI = 9 V to 26 V,
IO = 10 mA,
TJ = 0
C to 125
C
1
2
mA
Input bias current
ENABLE > 2 V
0.5
mA
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a 0.1-
F capacitor across the input and a 10-
F capacitor, with equivalent
series resistance of less than 0.4
, across the output.
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, V
I
= 14 V, I
O
= 10 mA, T
J
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TL750L10
TL751L10
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
VI = 11 V to 26 V,
IO = 0 to 150 mA
TJ = 25
C
9.6
10
10.4
V
Output voltage
VI = 11 V to 26 V,
IO = 0 to 150 mA
TJ = 0
C to 125
C
9.5
10.5
V
Input regulation voltage
VI = 12 V to 19 V
10
25
mV
Input regulation voltage
VI = 11 V to 26 V
30
60
mV
Ripple rejection
VI = 12 V to 22 V,
f = 120 Hz
60
65
dB
Output regulation voltage
IO = 5 mA to 150 mA
50
100
mV
Dropout voltage
IO = 10 mA
0.2
V
Dropout voltage
IO = 150 mA
0.6
V
Output noise voltage
f = 10 Hz to 100 kHz
700
V
IO = 150 mA
10
12
Input bias current
VI = 11 V to 26 V,
IO = 10 mA,
TJ = 0
C to 125
C
1
2
mA
Input bias current
ENABLE > 2 V
0.5
mA
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a 0.1-
F capacitor across the input and a 10-
F capacitor, with equivalent
series resistance of less than 0.4
, across the output.
electrical characteristics, V
I
= 14 V, I
O
= 10 mA, T
J
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TL750L12
TL751L12
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
VI = 13 V to 26 V,
IO = 0 to 150 mA
TJ = 25
C
11.52
12
12.48
V
Output voltage
VI = 13 V to 26 V,
IO = 0 to 150 mA
TJ = 0
C to 125
C
11.4
12.6
V
Input regulation voltage
VI = 14 V to 19 V
15
30
mV
Input regulation voltage
VI = 13 V to 26 V
20
40
mV
Ripple rejection
VI = 13 V to 23 V,
f = 120 Hz
50
55
dB
Output regulation voltage
IO = 5 mA to 150 mA
50
120
mV
Dropout voltage
IO = 10 mA
0.2
V
Dropout voltage
IO = 150 mA
0.6
V
Output noise voltage
f = 10 Hz to 100 kHz
700
V
IO = 150 mA
10
12
Input bias current
VI = 13 V to 26 V,
IO = 10 mA,
TJ = 0
C to 125
C
1
2
mA
Input bias current
ENABLE > 2 V
0.5
mA
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a 0.1-
F capacitor across the input and a 10-
F capacitor, with equivalent
series resistance of less than 0.4
, across the output.
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
30
20
0
100
200
40
TRANSIENT INPUT VOLTAGE
vs
TIME
60
300
400
500
600
i
V - T
ransient Input V
oltage - V
0
10
50
tr = 1 ms
TA = 25
C
VI = 14 V + 46e(-t/0.230)
for t
5 ms
t - Time - ms
Figure 1
Figure 2
20
15
5
0
0
1
2
3
- Input Current - mA
25
35
40
4
5
6
30
10
TL750L05
INPUT CURRENT
vs
INPUT VOLTAGE
I
I
VI - Input Voltage - V
30
20
10
0
0
2
4
40
50
60
6
8
12
14
10
VI - Input Voltage - V
TL750L12
INPUT CURRENT
vs
INPUT VOLTAGE
- Input Current - mA
I
I
Figure 3
TL750L, TL751L SERIES
LOW DROPOUT VOLTAGE REGULATORS
SLVS017R - SEPTEMBER 1987 - REVISED AUGUST 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
IL - Load Current - mA
TL750L05
EQUIVALENT SERIES RESISTANCE
vs
LOAD CURRENT
0.2
0.1
0
0
10
ESR - Equivalent Series Resistance -
0.3
0.4
0.5
0.024
0.6
0.7
0.8
0.9
1.0
Region of Best Stability
80
120
150
Potential Instability Region
CL = 10-
F Tantalum Capacitor
TA = - 40
C to 125
C
Potential Instability Region
Figure 4
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0
15
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA
MPFM001E OCTOBER 1994 REVISED JANUARY 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
KTE (R-PSFM-G3)
PowerFLEX
TM
PLASTIC FLANGE-MOUNT
0.360 (9,14)
0.350 (8,89)
0.080 (2,03)
0.070 (1,78)
0.010 (0,25) NOM
0.040 (1,02)
Seating Plane
0.050 (1,27)
0.001 (0,03)
0.005 (0,13)
0.010 (0,25)
NOM
Gage Plane
0.010 (0,25)
0.031 (0,79)
0.041 (1,04)
4073375/F 12/00
NOM
3
1
0.350 (8,89)
0.220 (5,59)
0.360 (9,14)
0.295 (7,49)
NOM
0.320 (8,13)
0.310 (7,87)
0.025 (0,63)
0.031 (0,79)
Thermal Tab
(See Note C)
0.004 (0,10)
M
0.010 (0,25)
0.100 (2,54)
3
6
0.410 (10,41)
0.420 (10,67)
0.200 (5,08)
0.365 (9,27)
0.375 (9,52)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The center lead is in electrical contact with the thermal tab.
D. Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).
E. Falls within JEDEC MO-169
PowerFLEX is a trademark of Texas Instruments.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MSOT002A OCTOBER 1994 REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
4040001-2 /C 10/01
STRAIGHT LEAD OPTION
0.016 (0,41)
0.014 (0,35)
0.157 (4,00) MAX
FORMED LEAD OPTION
0.104 (2,65)
0.210 (5,34)
0.170 (4,32)
0.050 (1,27)
0.016 (0,41)
0.022 (0,56)
0.500 (12,70) MIN
Seating
Plane
0.175 (4,44)
0.205 (5,21)
0.165 (4,19)
0.125 (3,17)
DIA
D
C
0.105 (2,67)
0.095 (2,41)
0.135 (3,43) MIN
0.080 (2,03)
0.055 (1,40)
0.045 (1,14)
1
0.105 (2,67)
2
3
0.080 (2,03)
0.105 (2,67)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area
D. FAlls within JEDEC TO -226 Variation AA (TO-226 replaces TO-92)
E. Shipping Method:
Straight lead option available in bulk pack only.
Formed lead option available in tape & reel or ammo pack.
MECHANICAL DATA
MSOT002A OCTOBER 1994 REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
4040001-3 /C 10/01
0.094 (2,40)
0.114 (2,90)
0.460 (11,70)
0.539 (13,70)
TAPE & REEL
0.335 (8,50)
0.384 (9,75)
0.020 (0,50) MIN
0.217 (5,50)
0.748 (19,00)
0.748 (19,00)
0.689 (17,50)
0.098 (2,50)
0.433 (11,00)
0.335 (8,50)
0.610 (15,50)
0.650 (16,50)
1.260 (32,00)
0.905 (23,00)
0.234 (5,95)
0.266 (6,75)
0.512 (13,00)
0.488 (12,40)
0.114 (2,90)
0.094 (2,40)
0.146 (3,70)
0.169 (4,30)
DIA
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Tape and Reel information for the Format Lead Option package.
MECHANICAL DATA
MSOT007A JANUARY 1995 REVISED SEPTEMBER 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
KC (R-PSFM-T3)
PLASTIC FLANGE-MOUNT PACKAGE
4040207 / B 01/95
(see Note F)
0.185 (4,70)
0.270 (6,86)
0.230 (5,84)
0.175 (4,46)
(see Note H)
0.052 (1,32)
0.048 (1,22)
0.122 (3,10)
0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
0.420 (10,67)
MAX
0.250 (6,35)
0.380 (9,65)
(see Note H)
0.146 (3,71)
0.156 (3,96)
DIA
0.125 (3,18)
(see Note C)
3
0.070 (1,78)
0.045 (1,14)
1
0.035 (0,89)
0.029 (0,74)
0.625 (15,88)
0.562 (14,27)
0.500 (12,70)
0.560 (14,22)
0.120 (3,05)
0.100 (2,54)
0.100 (2,54)
M
0.010 (0,25)
0.200 (5,08)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area.
D. All lead dimensions apply before solder dip.
E. The center lead is in electrical contact with the mounting tab.
F. The chamfer is optional.
G. Falls within JEDEC TO-220AB
H. Tab contour optional within these dimensions
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