SN54ACT10, SN74ACT10
TRIPLE 3 INPUT POSITIVE NAND GATES
SCAS526C - AUGUST 1995 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
4.5-V to 5.5-V V
CC
Operation
D
Inputs Accept Voltages to 5.5 V
D
Max t
pd
of 9.5 ns at 5 V
D
Inputs Are TTL-Voltage Compatible
SN54ACT10 . . . J OR W PACKAGE
SN74ACT10 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
2C
2Y
GND
V
CC
1C
1Y
3A
3B
3C
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y
NC
3A
NC
3B
2A
NC
2B
NC
2C
SN54ACT10 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
3Y
3C
V
1C
2Y
GND
NC
NC - No internal connection
CC
description/ordering information
The 'ACT10 devices contain three independent 3-input NAND gates. The devices perform the Boolean
functions Y = A
B
C or Y = A + B + C in positive logic.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube
SN74ACT10N
SN74ACT10N
SOIC - D
Tube
SN74ACT10D
ACT10
SOIC - D
Tape and reel
SN74ACT10DR
ACT10
-40
C to 85
C
SOP - NS
Tape and reel
SN74ACT10NSR
ACT10
-40 C to 85 C
SSOP - DB
Tape and reel
SN74ACT10DBR
AD10
TSSOP - PW
Tube
SN74ACT10PW
AD10
TSSOP - PW
Tape and reel
SN74ACT10PWR
AD10
CDIP - J
Tube
SNJ54ACT10J
SNJ54ACT10J
-55
C to 125
C
CFP - W
Tube
SNJ54ACT10W
SNJ54ACT10W
-55 C to 125 C
LCCC - FK
Tube
SNJ54ACT10FK
SNJ54ACT10FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ACT10, SN74ACT10
TRIPLE 3 INPUT POSITIVE NAND GATES
SCAS526C - AUGUST 1995 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram, each gate (positive logic)
12
1Y
1A
1B
1C
6
2Y
2A
2B
2C
8
3Y
3A
3B
3C
1
2
13
3
4
5
11
10
9
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT10
SN74ACT10
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
-24
-24
mA
IOL
Low-level output current
24
24
mA
t/
v
Input transition rise or fall rate
8
8
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54ACT10, SN74ACT10
TRIPLE 3 INPUT POSITIVE NAND GATES
SCAS526C - AUGUST 1995 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54ACT10
SN74ACT10
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = -50 A
4.5 V
4.4
4.49
4.4
4.4
IOH = -50
A
5.5 V
5.4
5.49
5.4
5.4
VOH
IOH = -24 mA
4.5 V
3.86
3.7
3.76
V
VOH
IOH = -24 mA
5.5 V
4.86
4.7
4.76
V
IOH = -50 mA
5.5 V
3.85
IOH = -75 mA
5.5 V
3.85
IOL = 50 A
4.5 V
0.001
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.001
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.6
1.6
1.5
mA
Ci
VI = VCC or GND
5 V
2.6
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
"
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
SN54ACT10
SN74ACT10
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
Any
Y
1
6.5
9
1
10
1
10
ns
tPHL
Any
Y
1
6.5
9
1
9.5
1
9.5
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
25
pF
SN54ACT10, SN74ACT10
TRIPLE 3 INPUT POSITIVE NAND GATES
SCAS526C - AUGUST 1995 - REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Open
TEST
tPLH/tPHL
S1
Open
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
v
2.5 ns, tf
v
2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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