CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29520
D
Reduced V
OH
(Typically = 3.3 V) Version of
Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Matched Rise and Fall Times
D
Fully Compatible With TTL Input and
Output Logic Levels
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
D
Single- and Dual-Pipeline Operation Modes
D
Multiplexed Data Inputs and Outputs
D
CY29FCT520T
64-mA Output Sink Current
32-mA Output Source Current
D
CY29FCT520ATDMB, CY29FCT520BTDMB
32-mA Output Sink Current
12-mA Output Source Current
D
3-State Outputs
description
The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1,
and B2, which are configured by the instruction inputs I
0
, I
1
as a single four-level pipeline or as two two-level
pipelines. The contents of any register can be read at the multiplexed output at any time by using the
multiplex-selection controls (S
0
and S
1
).
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input.
Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2
selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I
0
I
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLK
GND
D, P, OR SO PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
OE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PIPELINE INSTRUCTION TABLE
I = 0
I = 1
I = 2
I = 3
I1 = 0
I0 = 0
I1 = 0
I0 = 1
I1 = 1
I0 = 0
I1 = 1
I0 = 1
A1
A2
B1
B2
A1
A2
B1
B2
A1
A2
B1
B2
B1
B2
A1
A2
Single four-level
Dual two-level
Hold
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC
SO
Tube
6.0
CY29FCT520CTSOC
29FCT520C
SOIC SO
Tape and reel
6.0
CY29FCT520CTSOCT
29FCT520C
SOIC
SO
Tube
7.5
CY29FCT520BTSOC
29FCT520B
40
C to 85
C
SOIC SO
Tape and reel
7.5
CY29FCT520BTSOCT
29FCT520B
DIP P
Tube
14.0
CY29FCT520ATPC
CY29FCT520ATPC
SOIC
SO
Tube
14.0
CY29FCT520ATSOC
29FCT520A
SOIC SO
Tape and reel
14.0
CY29FCT520ATSOCT
29FCT520A
55
C to 125
C
CDIP
D
Tube
8.0
5962-9220504MLA
(CY29FCT520BTDMB)
55
C to 125
C
CDIP D
Tube
16.0
5962-9220502MLA
(CY29FCT520ATDMB)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
S1
S0
OUTPUT
1
1
A1
1
0
A2
0
1
B1
0
0
B2
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram
MUX
MUX
Octal Register
A1
Register
Controls
Instruction
I0
I1
CLK
S0
S1
D0D7
Y0Y7
OE
Octal Register
A2
Octal Register
B1
Octal Register
B2
MUX
8
8
Selection
Multiplex
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin)
120 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): P package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SO package
46
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, T
A
65
C to 135
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
CY29FCT520ATDMB
CY29FCT520BTDMB
CY29FCT520T
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
12
32
mA
IOL
Low-level output current
32
64
mA
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY29FCT520ATDMB
CY29FCT520BTDMB
CY29FCT520T
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
IIN = 18 mA
0.7
1.2
V
VIK
VCC = 4.75 V,
IIN = 18 mA
0.7
1.2
V
VCC = 4.5 V,
IOH = 12 mA
2.4
3.3
VOH
VCC = 4 75 V
IOH = 15 mA
2.4
3.3
V
VCC = 4.75 V
IOH = 32 mA
2
VOL
VCC = 4.5 V,
IOL = 32 mA
0.3
0.55
V
VOL
VCC = 4.75 V,
IOL = 64 mA
0.3
0.55
V
Vhys
All inputs
0.2
0.2
V
II
VCC = 5.5 V,
VIN = VCC
5
A
II
VCC = 5.25 V,
VIN = VCC
5
A
IIH
VCC = 5.5 V,
VIN = 2.7 V
1
A
IIH
VCC = 5.25 V,
VIN = 2.7 V
1
A
IIL
VCC = 5.5 V,
VIN = 0.5 V
1
A
IIL
VCC = 5.25 V,
VIN = 0.5 V
1
A
Ioff
VCC = 0 V,
VOUT = 4.5 V
1
1
A
I
VCC = 5.5 V,
VOUT = 0 V
60
120
225
mA
IOS
VCC = 5.25 V,
VOUT = 0 V
60
120
225
mA
IOZH
VCC = 5.5 V,
VIN = 2.7 V
10
A
IOZH
VCC = 5.25 V,
VIN = 2.7 V
10
A
IOZL
VCC = 5.5 V,
VIN = 0.5 V
10
A
IOZL
VCC = 5.25 V,
VIN = 0.5 V
10
A
ICC
VCC = 5.5 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.25 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.5 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
ICC
VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
Typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, IOS tests should be performed last.
Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY29FCT520ATDMB
CY29FCT520BTDMB
CY29FCT520T
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
I
VCC = 5.5 V, Outputs open,
One bit switching at 50% duty cycle, OE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
mA/
ICCD
VCC = 5.25 V, Outputs open,
One bit switching at 50% duty cycle, OE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
MHz
#
One bit switching
at f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
#
VCC = 5.5 V,
Outputs open
1
50% duty cycle
VIN = 3.4 V or GND
1.2
3.4
#
Out uts o en,
f0 = 10 MHz,
OE = GND
Eight bits
switching at
f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
2.8
5.6||
IC#
f1 = 5 MHz at
50% duty cycle
VIN = 3.4 V or GND
5.1
14.3||
mA
IC#
One bit switching
at f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
mA
VCC = 5.25 V,
Outputs open
1
50% duty cycle
VIN = 3.4 V or GND
1.2
3.4
Out uts o en,
f0 = 10 MHz,
OE = GND
Eight bits
switching at
f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
2.8
5.6||
f1 = 5 MHz at
50% duty cycle
VIN = 3.4 V or GND
5.1
14.3||
Ci
5
10
5
10
pF
Co
9
12
9
12
pF
Typical values are at VCC = 5 V, TA = 25
C.
This parameter is derived for use in total power-supply calculations.
# IC
= ICC +
ICC
DH
NT + ICCD (f0/2 + f1
N1)
Where:
IC
= Total supply current
ICC
= Power-supply current with CMOS input levels
ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY29FCT520ATDMB
CY29FCT520BTDMB
UNIT
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, CLK high or low
8
6
ns
t
S t
ti
b f
CLK
Data
6
2.8
ns
tsu
Setup time, before CLK
I
6
4.5
ns
th
Hold time after CLK
Data
2
2
ns
th
Hold time, after CLK
I
2
2
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY29FCT520AT
CY29FCT520BT
CY29FCT520CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, CLK high or low
7
5.5
5.5
ns
t
S t
ti
b f
CLK
Data
5
2.5
2.5
ns
tsu
Setup time, before CLK
I
5
4
4
ns
th
Hold time after CLK
Data
2
2
2
ns
th
Hold time, after CLK
I
2
2
2
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
TO
CY29FCT520ATDMB
CY29FCT520BTDMB
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tPLH
CLK
Y
2
16
2
8
ns
tPHL
CLK
Y
2
16
2
8
ns
tPLH
S0 or S1
Y
2
15
2
8
ns
tPHL
S0 or S1
Y
2
15
2
8
ns
tPHZ
OE
Y
1.5
13
1.5
7.5
ns
tPLZ
OE
Y
1.5
13
1.5
7.5
ns
tPZH
OE
Y
1.5
16
1.5
8
ns
tPZL
OE
Y
1.5
16
1.5
8
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
TO
CY29FCT520AT
CY29FCT520BT
CY29FCT520CT
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
CLK
Y
2
14
2
7.5
2
6
ns
tPHL
CLK
Y
2
14
2
7.5
2
6
ns
tPLH
S0 or S1
Y
2
13
2
7.5
2
6
ns
tPHL
S0 or S1
Y
2
13
2
7.5
2
6
ns
tPHZ
OE
Y
1.5
12
1.5
7
1.5
6
ns
tPLZ
OE
Y
1.5
12
1.5
7
1.5
6
ns
tPZH
OE
Y
1.5
15
1.5
7.5
1.5
6
ns
tPZL
OE
Y
1.5
15
1.5
7.5
1.5
6
ns
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C MAY 1994 REVISED NOVEMBER 2001
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL
+ 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1
7 V
500
GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
0.3 V
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9220502MLA
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
5962-9220504MLA
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
CY29FCT520ATPC
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CY29FCT520ATPCE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CY29FCT520ATSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520ATSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520ATSOCT
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520ATSOCTE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520BTSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520BTSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520BTSOCT
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520BTSOCTE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520CTSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520CTSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520CTSOCT
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT520CTSOCTE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
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21-Nov-2005
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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21-Nov-2005
Addendum-Page 2
MECHANICAL DATA
MCER004A JANUARY 1995 REVISED JANUARY 1997
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0
15
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN
(6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MPDI004 OCTOBER 1994
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
4040050 / B 04/95
24 PINS SHOWN
1.425
(36,20)
1.385
0.295
(7,49)
(8,00)
0.315
(35,18)
28
PINS **
A MIN
A MAX
B MAX
B MIN
13
0.250 (6,35)
0.280 (7,11)
12
0.200 (5,08) MAX
DIM
24
1.230
(31,24)
(32,04)
1.260
0.310
(7,87)
(7,37)
0.290
B
0.125 (3,18) MIN
Seating Plane
0.010 (0,25) NOM
A
0.070 (1,78) MAX
24
1
0.015 (0,38)
0.021 (0,53)
0.020 (0,51) MIN
0.100 (2,54)
M
0.010 (0,25)
0
15
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
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