CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Function and Pinout Compatible With FCT
and F Logic
D
Reduced V
OH
(Typically = 3.3 V) Versions
of Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
I
off
Supports Partial-Power-Down Mode
Operation
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
D
Matched Rise and Fall Times
D
Fully Compatible With TTL Input and
Output Logic Levels
D
3-State Outputs
D
CY54FCT373T
32-mA Output Sink Current
12-mA Output Source Current
D
CY74FCT373T
64-mA Output Sink Current
32-mA Output Source Current
description
The 'FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
CY54FCT373T . . . D PACKAGE
CY74FCT373T . . . Q OR SO PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q
Tape and reel
4.7
CY74FCT373CTQCT
FCT373C
SOIC
SO
Tube
4.7
CY74FCT373CTSOC
FCT373C
SOIC SO
Tape and reel
4.7
CY74FCT373CTSOCT
FCT373C
40
C to 85
C
QSOP Q
Tape and reel
5.2
CY74FCT373ATQCT
FCT373A
40
C to 85
C
SOIC
SO
Tube
5.2
CY74FCT373ATSOC
FCT373
SOIC SO
Tape and reel
5.2
CY74FCT373ATSOCT
FCT373
SOIC
SO
Tube
8
CY74FCT373TSOC
FCT373
SOIC SO
Tape and reel
8
CY74FCT373TSOCT
FCT373
55
C to 125
C
CDIP D
Tube
5.6
CY54FCT373ATDMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
H = High logic level, L = Low logic level,
X = Don't care, Z = High-impedance state,
Qn = Previous state of flip flops (Qn1)
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
LE
D0
CP
D
O0
Q
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin)
120 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): Q package
68
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, T
A
65
C to 135
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT373T
CY74FCT373T
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
12
32
mA
IOL
Low-level output current
32
64
mA
TA
Operating free-air temperature
55
125
40
85
C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY54FCT373T
CY74FCT373T
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
IIN = 18 mA
0.7
1.2
V
VIK
VCC = 4.75 V,
IIN = 18 mA
0.7
1.2
V
VCC = 4.5 V,
IOH = 12 mA
2.4
3.3
VOH
VCC 4 75 V
IOH = 32 mA
2
V
VCC = 4.75 V
IOH = 15 mA
2.4
3.3
VOL
VCC = 4.5 V,
IOL = 32 mA
0.3
0.55
V
VOL
VCC = 4.75 V,
IOL = 64 mA
0.3
0.55
V
Vhys
All inputs
0.2
0.2
V
II
VCC = 5.5 V,
VIN = VCC
5
A
II
VCC = 5.25 V,
VIN = VCC
5
A
IIH
VCC = 5.5 V,
VIN = 2.7 V
1
A
IIH
VCC = 5.25 V,
VIN = 2.7 V
1
A
IIL
VCC = 5.5 V,
VIN = 0.5 V
1
A
IIL
VCC = 5.25 V,
VIN = 0.5 V
1
A
IOZH
VCC = 5.5 V,
VOUT = 2.7 V
10
A
IOZH
VCC = 5.25 V,
VOUT = 2.7 V
10
A
IOZL
VCC = 5.5 V,
VOUT = 0.5 V
10
A
IOZL
VCC = 5.25 V,
VOUT = 0.5 V
10
A
IOS
VCC = 5.5 V,
VOUT = 0 V
60
120
225
mA
IOS
VCC = 5.25 V,
VOUT = 0 V
60
120
225
mA
Ioff
VCC = 0 V,
VOUT = 4.5 V
1
1
A
ICC
VCC = 5.5 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.25 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.5 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
ICC
VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
Typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT373T
CY74FCT373T
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ICCD
VCC = 5.5 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
mA/
ICCD
VCC = 5.25 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
MHz
#
VCC = 5 5 V
One bit switching
at f1 = 10 MHz
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
#
VCC = 5.5 V,
Outputs open,
1
at 50% duty cycle
VIN = 3.4 V or GND
1
2.4
#
,
OE = GND,
LE = VCC
Eight bits switching
at f1 = 2.5 MHz
VIN
0.2 V or
VIN
VCC 0.2 V
1.3
2.6||
IC#
1
at 50% duty cycle
VIN = 3.4 V or GND
3.3
10.6||
mA
IC#
VCC = 5 25 V
One bit switching
at f1 = 10 MHz
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
mA
VCC = 5.25 V,
Outputs open,
1
at 50% duty cycle
VIN = 3.4 V or GND
1
2.4
,
OE = GND,
LE = VCC
Eight bits switching
at f1 = 2.5 MHz
VIN
0.2 V or
VIN
VCC 0.2 V
1.3
2.6||
1
at 50% duty cycle
VIN = 3.4 V or GND
3.3
10.6||
Ci
6
10
6
10
pF
Co
8
12
8
12
pF
Typical values are at VCC = 5 V, TA = 25
C.
This parameter is derived for use in total power-supply calculations.
# IC
= ICC +
ICC
DH
NT + ICCD (f0/2 + f1
N1)
Where:
IC
= Total supply current
ICC
= Power-supply current with CMOS input levels
ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT373T
CY54FCT373AT
UNIT
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
6
6
ns
tsu
Setup time, data before LE
2
2
ns
th
Hold time, data after LE
1.5
1.5
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT373T
CY74FCT373AT
CY74FCT373CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
6
5
5
ns
tsu
Setup time, data before LE
2
2
2
ns
th
Hold time, data after LE
1.5
1.5
1.5
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
TO
CY54FCT373AT
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
UNIT
tPLH
D
O
1.5
5.6
ns
tPHL
D
O
1.5
5.6
ns
tPLH
LE
O
2
9.8
ns
tPHL
LE
O
2
9.8
ns
tPZH
OE
O
1.5
7.5
ns
tPZL
OE
O
1.5
7.5
ns
tPHZ
OE
O
1.5
6.5
ns
tPLZ
OE
O
1.5
6.5
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
TO
CY74FCT373T
CY74FCT373AT
CY74FCT373CT
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
D
O
1.5
8
1.5
5.2
1.5
4.7
ns
tPHL
D
O
1.5
8
1.5
5.2
1.5
4.7
ns
tPLH
LE
O
2
13
2
8.5
2
5.5
ns
tPHL
LE
O
2
13
2
8.5
2
5.5
ns
tPZH
OE
O
1.5
12
1.5
6.5
1.5
5.5
ns
tPZL
OE
O
1.5
12
1.5
6.5
1.5
5.5
ns
tPHZ
OE
O
1.5
7.5
1.5
5.5
1.5
5
ns
tPLZ
OE
O
1.5
7.5
1.5
5.5
1.5
5
ns
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MAY 1994 REVISED OCTOBER 2001
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL
+ 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1
7 V
500
GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
0.3 V
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Post Office Box 655303
Dallas, Texas 75265
Copyright
2001, Texas Instruments Incorporated
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