SN54ABT377, SN74ABT377
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156B FEBRUARY 1991 REVISED JULY 1994
Copyright
1994, Texas Instruments Incorporated
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
C
High-Drive Outputs ( 32-mA I
OH
,
64-mA I
OL
)
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
description
The
ABT377 are 8-bit positive-edge-triggered
D-type flip-flops with a clock (CLK) input. They are
particularly suitable for implementing buffer and
storage registers, shift registers, and pattern
generators.
Data (D) input information that meets the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse if the
common clock-enable (CLKEN) input is low. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the buffered clock
(CLK) input is at either the high or low level, the
D input signal has no effect at the output. The
circuits are designed to prevent false clocking by
transitions at CLKEN.
The SN74ABT377 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT377 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74ABT377 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLKEN
CLK
D
Q
H
X
X
Q0
L
H
H
L
L
L
X
H or L
X
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKEN
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ABT377 . . . J PACKAGE
SN74ABT377 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
SN54ABT377 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
CLKEN
5Q
5D
8Q
4Q
GND
CLK
V
CC
8D
7D
7Q
6Q
6D
EPIC-
B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ABT377, SN74ABT377
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156B FEBRUARY 1991 REVISED JULY 1994
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
13
5D
14
6D
17
7D
18
8D
1Q
2
2Q
5
3Q
6
4Q
9
1C2
CE
G1
1
11
CLK
2D
3
1D
4
2D
7
3D
8
4D
5Q
12
6Q
15
7Q
16
8Q
19
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
11
1Q
1D
C1
CLK
CLKEN
1
3
2
To Seven Other Channels
SN54ABT377, SN74ABT377
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156B FEBRUARY 1991 REVISED JULY 1994
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT377
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT377
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): DB package
0.6 W
. . . . . . . . . . . . . . . . . . . .
DW package
1.6 W
. . . . . . . . . . . . . . . . . . .
N package
1.3 W
. . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT377
SN74ABT377
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t /
v
Input transition rise or fall rate
5
5
ns / V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused or floating inputs must be held high or low.
SN54ABT377, SN74ABT377
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156B FEBRUARY 1991 REVISED JULY 1994
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT377
SN74ABT377
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
II
VCC = 5.5 V,
VI = VCC or GND
1
1
1
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
100
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
100
180
50
180
50
180
mA
ICC
VCC = 5.5 V,
IO = 0,
Outputs high
1
250
250
250
A
ICC
CC
,
O
,
VI = VCC or GND
Outputs low
24
30
30
30
mA
ICC
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
mA
Ci
VI = 2.5 V or 0.5 V
3
pF
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
All typical values are at VCC = 5 V.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25
C
SN54ABT377
SN74ABT377
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
150
0
150
0
150
MHz
tw
Pulse duration
CLK high or low
3.3
3.3
3.3
ns
t
Setup time before CLK
Data high or low
2
2.5
2
ns
tsu
Setup time before CLK
CLKEN high or low
3
3
3
ns
th
Hold time after CLK
Data high or low
1.8
1.8
1.8
ns
th
Hold time after CLK
CLKEN high or low
1.8
1.8
1.8
ns
This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54ABT377
SN74ABT377
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
150
150
150
MHz
tPLH
CLK
Q
2.2
4.5
6
2.2
7
2.2
6.5
ns
tPHL
CLK
Q
3.1
5.3
6.8
2
7.6
3.1
7.3
ns
SN54ABT377, SN74ABT377
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156B FEBRUARY 1991 REVISED JULY 1994
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
(see Note B)
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH 0.3 V
[
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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