SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
C
D
High-Drive Outputs (32-mA I
OH
, 64-mA I
OL
)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select either real-time or stored data for
transfer. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the 'ABT652A.
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
B is a trademark of Texas Instruments Incorporated.
SN54ABT652A . . . JT OR W PACKAGE
SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
SN54ABT652A . . . FK PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
OEBA
B1
B2
NC
B3
B4
B5
A1
A2
A2
NC
A4
A5
A6
4
26
14 15 16 17 18
A7
A8
GND
NC
B8
B7
B6
OEAB
SAB
CLKAB
NC
CLKBA
SBA
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
NC No internal connection
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The SN54ABT652A is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74ABT652A is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1A8
B1B8
OPERATION OR FUNCTION
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
H or L
X
X
Input
Unspecified
Store A, hold B
H
H
X
X
Input
Output
Store A in both registers
L
X
H or L
X
X
Unspecified
Input
Hold A, store B
L
L
X
X
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
L
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
CLKAB
X
CLKBA
X
SAB
L
SBA
X
H
CLKAB CLKBA
X
SAB
X
SBA
X
CLKAB
CLKBA
SAB
SBA
X
H
X
X
X
X
X
H
L
H or L
H
H
OEBA
OEBA
H
H
OEAB OEBA
OEAB
OEBA
H or L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
3
21
1
23
2
22
1
23
2
22
3
21
3
21
23
2
22
3
21
1
2
22
1
23
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
Figure 1. Bus-Management Functions
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
OEBA
EN1 [BA]
21
G5
22
SBA
A1
4
B1
20
4D
EN2 [AB]
3
OEAB
23
CLKBA
1
CLKAB
G7
2
SAB
5
7
7
5
6D
1
1
2
C6
C4
A2
5
B2
19
A3
6
B3
18
A4
7
B4
17
A5
8
B5
16
A6
9
B6
15
A7
10
B7
14
A8
11
B8
13
1
1
1
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
OEBA
A1
B1
1D
C1
1D
C1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
21
3
23
22
1
2
4
20
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(except I/O ports) (see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT652A 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT652A
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
104
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
81
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
120
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT652A
SN74ABT652A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
5
5
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT652A
SN74ABT652A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
Control inputs
VCC = 5 5 V
VI = VCC or GND
1
1
1
A
II
A or B ports
VCC = 5.5 V,
VI = VCC or GND
100
100
100
A
IOZH
VCC = 5.5 V,
VO = 2.7 V
50**
10
50
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
50**
10
50
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
100
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
100
180
50
180
50
180
mA
VCC = 5.5 V,
Outputs high
250
250
250
A
ICC
VCC = 5.5 V,
IO = 0,
Outputs low
30
30
30
mA
VI = VCC or GND
Outputs disabled
250
250
250
A
ICC
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
mA
Ci
Control inputs
VI = 2.5 V or 0.5 V
7
pF
Cio
A or B ports
VO = 2.5 V or 0.5 V
12
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT652A.
All typical values are at VCC = 5 V.
The parameters IOZH and IOZL include the input leakage current.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT652A
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
fclock
Clock frequency
0
125
0
125
MHz
tw
Pulse duration, CLK high or low
4
4
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
3
3.5
ns
th
Hold time, A or B after CLKAB
or CLKBA
1.5
1.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT652A
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
fclock
Clock frequency
0
125
0
125
MHz
tw
Pulse duration, CLK high or low
4
4
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
3
3
ns
th
Hold time, A or B after CLKAB
or CLKBA
0
0
ns
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
TYP
MAX
fmax
125
200
125
MHz
tPLH
CLK
B or A
2.2
4
5.1
1.7
5.9
ns
tPHL
CLK
B or A
1.7
4
5.1
1.7
5.9
ns
tPLH
A or B
B or A
1.5
3
4.8
1
5
ns
tPHL
A or B
B or A
1.5
3.3
4.6
1
5.6
ns
tPLH
SAB or SBA
B or A
1.5
4
5.5
1.5
6.8
ns
tPHL
SAB or SBA
B or A
1.5
3.6
4.9
1.5
6.2
ns
tPZH
OEBA
A
2
3.6
5.4
2
6.8
ns
tPZL
OEBA
A
3
5.7
7.7
3
9.2
ns
tPHZ
OEBA
A
1.5
3.2
5.8
1
7.5
ns
tPLZ
OEBA
A
1.5
3
4.3
1
4.6
ns
tPZH
OEAB
B
2
4.3
6.1
2
7.8
ns
tPZL
OEAB
B
3
5.5
7.4
3
8.9
ns
tPHZ
OEAB
B
1.5
3.3
6
1
8
ns
tPLZ
OEAB
B
1.5
3.4
5
1.5
6.8
ns
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
TYP
MAX
fmax
125
200
125
MHz
tPLH
CLK
B or A
2.2
4
5.1
2.2
5.6
ns
tPHL
CLK
B or A
1.7
4
5.1
1.7
5.6
ns
tPLH
A or B
B or A
1.5
3
4.3
1.5
4.8
ns
tPHL
A or B
B or A
1.5
3.3
4.6
1.5
5.4
ns
tPLH
SAB or SBA
B or A
1.5
4
5.1
1.5
6.5
ns
tPHL
SAB or SBA
B or A
1.5
3.6
4.9
1.5
5.9
ns
tPZH
OEBA
A
2
3.6
4.6
2
5.8
ns
tPZL
OEBA
A
3
5.7
6.8
3
8.5
ns
tPHZ
OEBA
A
1.5
3.2
4.5
1.5
5
ns
tPLZ
OEBA
A
1.5
3
3.8
1.5
4.1
ns
tPZH
OEAB
B
2
4.3
6.1
2
6.5
ns
tPZL
OEAB
B
3
5.5
6.5
3
7.4
ns
tPHZ
OEAB
B
1.5
3.3
4.5
1.5
5.5
ns
tPLZ
OEAB
B
1.5
3.4
4.4
1.5
5.1
ns
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9324202Q3A
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
5962-9324202QKA
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
5962-9324202QLA
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
SN74ABT652ADBLE
OBSOLETE
SSOP
DB
24
TBD
Call TI
Call TI
SN74ABT652ADBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADBRE4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANSR
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANSRE4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ABT652ANTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SNJ54ABT652AFK
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT652AJT
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT652AW
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 1
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 2
MECHANICAL DATA
MCER004A JANUARY 1995 REVISED JANUARY 1997
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0
15
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN
(6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 OCTOBER 1994
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
4040180-5 / B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
1
24
0.360 (9,14)
0.240 (6,10)
13
12
Base and Seating Plane
30
TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI004 OCTOBER 1994
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
4040050 / B 04/95
24 PINS SHOWN
1.425
(36,20)
1.385
0.295
(7,49)
(8,00)
0.315
(35,18)
28
PINS **
A MIN
A MAX
B MAX
B MIN
13
0.250 (6,35)
0.280 (7,11)
12
0.200 (5,08) MAX
DIM
24
1.230
(31,24)
(32,04)
1.260
0.310
(7,87)
(7,37)
0.290
B
0.125 (3,18) MIN
Seating Plane
0.010 (0,25) NOM
A
0.070 (1,78) MAX
24
1
0.015 (0,38)
0.021 (0,53)
0.020 (0,51) MIN
0.100 (2,54)
M
0.010 (0,25)
0
15
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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amplifier.ti.com
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