SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E JANUARY 1991 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
C
D
High-Impedance State During Power Up
and Power Down
D
High-Drive Outputs (32-mA I
OH
, 64-mA I
OL
)
D
Buffered Control Inputs to Reduce
dc Loading Effects
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK) and Flatpacks (W), and
Standard Plastic (NT) and Ceramic (JT)
DIPs
description
These 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
With the clock-enable (CLKEN) input low, the nine
D-type edge-triggered flip-flops enter data on the
low-to-high transitions of the clock. Taking CLKEN
high disables the clock buffer, thus latching the
outputs. Taking the clear (CLR) input low causes
the nine Q outputs to go low, independently of the
clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
When V
CC
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT823 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74ABT823 is characterized for operation from 40
C to 85
C.
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
B is a trademark of Texas Instruments Incorporated.
SN54ABT823 . . . JT OR W PACKAGE
SN74ABT823 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
SN54ABT823 . . . FK PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3Q
4Q
5Q
NC
6Q
7Q
8Q
3D
4D
5D
NC
6D
7D
8D
4
26
14 15 16 17 18
9D
CLR
GND
NC
CLK
CLKEN
9Q
2D
1D
OE
NC
1Q
2Q
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
NC No internal connection
SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E JANUARY 1991 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLR
CLKEN
CLK
D
Q
L
L
X
X
X
L
L
H
L
H
H
L
H
L
L
L
L
H
H
X
X
Q0
H
X
X
X
X
Z
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
EN
1
7
6D
8
7D
9
8D
10
9D
2D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
13
CLK
1C2
R
11
CLR
G1
14
CLKEN
SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E JANUARY 1991 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
To Eight Other Channels
1D
1Q
CLKEN
CLK
OE
CLR
1
11
14
13
2
R
1D
C1
23
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT823 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT823 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
104
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
81
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E JANUARY 1991 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABT823
SN74ABT823
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
5
5
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT823
SN74ABT823
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
VCC = 5.5 V,
VI = VCC or GND
1
1
1
A
IOZPU
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
50
50
50
A
IOZPD
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
50
50
50
A
IOZH
VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE
2 V
10
10
10
A
IOZL
VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE
2 V
10
10
10
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
100
A
ICEX
VCC = 5.5 V, VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
140
180
50
180
50
180
mA
V
5 5 V I
0
Outputs high
1
250
250
250
A
ICC
VCC = 5.5 V, IO = 0,
VI = VCC or GND
Outputs low
24
38
38
38
mA
VI = VCC or GND
Outputs disabled
0.5
250
250
250
A
ICC#
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
mA
Ci
VI = 2.5 V or 0.5 V
4
pF
Co
VO = 2.5 V or 0.5 V
7
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
All typical values are at VCC = 5 V.
This parameter is characterized, but not production tested.
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E JANUARY 1991 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25
C
SN54ABT823
SN74ABT823
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
125
0
125
0
125
MHz
CLR low
5.5
5.5
5.5
tw
Pulse duration
CLK high
2.9
2.9
2.9
ns
CLK low
3.8
3.8
3.8
CLR inactive
2.5
2.5
2.5
t
Setup time before CLK
Data
2.1
2.1
2.1
ns
tsu
Setup time before CLK
CLKEN high
2
2
2
ns
CLKEN low
3.3
3.3
3.3
Data
1.3
1.3
1.3
th
Hold time after CLK
CLKEN high
1
1
1
ns
CLKEN low
2
2
2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54ABT823
SN74ABT823
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
125
200
125
125
MHz
tPLH
CLK
Q
2.1
4.3
5.9
2.1
8.1
2.1
6.8
ns
tPHL
CLK
Q
2.2
4.4
6.1
2.2
7
2.2
6.7
ns
tPHL
CLR
Q
2
4.1
6.3
2
7.3
2
7.1
ns
tPZH
OE
Q
1
3
4.7
1
6.3
1
6
ns
tPZL
OE
Q
2.2
4.1
5.6
2.2
6.6
2.2
6.5
ns
tPHZ
OE
Q
2.7
4.8
6.5
2.7
7.7
2.7
7.5
ns
tPLZ
OE
Q
1.9
5
6.4
1.9
7.4
1.9
6.9
ns
This data sheet limit may vary among suppliers.
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