SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
C
D
High-Drive Outputs (32-mA I
OH
, 64-mA I
OL
)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on
the A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the 'ABT646A.
Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port can be stored in either
register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT646A is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74ABT646A is characterized for operation from 40
C to 85
C.
SN54ABT646A . . . JT OR W PACKAGE
SN74ABT646A . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2 1 28
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
SN54ABT646A . . . FK PACKAGE
(TOP VIEW)
DIR
SAB
CLKAB
B8
B7
A8
GND
NC
NC
CLKBA
SBA
V
A7
B6
17 18
27 26
CC
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC No internal connection
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-
B is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
21
X
3
DIR
X
1
CLKAB
23
CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
X
X
X
X
X
L
H
L
X
H
X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OE
OE
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
Figure 1. Bus-Management Functions
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1A8
B1B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
X
X
X
X
X
Unspecified
Input
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
logic symbol
OE
G3
21
3 EN2 [AB]
G5
22
SBA
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
A1
4
B1
20
4D
B2
19
B3
18
B4
17
B5
16
B6
15
B7
14
B8
13
3 EN1 [BA]
3
DIR
23
CLKBA
1
CLKAB
G7
2
SAB
5
7
7
5
1
1
6D
1
1
1
2
C6
C4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
One of Eight
Channels
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
21
3
23
22
1
2
4
20
1D
C1
1D
C1
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(except I/O ports) (see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT646A 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT646A
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
104
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
81
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
120
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT646A
SN74ABT646A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
5
5
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT646A
SN74ABT646A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
Control inputs
VCC = 5 5 V VI = VCC or GND
1
1
1
A
II
A or B ports
VCC = 5.5 V, VI = VCC or GND
100
100
100
A
IOZH
VCC = 5.5 V,
VO = 2.7 V
10
10
10
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
10
10
10
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
100
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
100
180
50
180
50
180
mA
VCC = 5.5 V,
Outputs high
250
250
250
A
ICC
VCC = 5.5 V,
IO = 0,
Outputs low
30
30
30
mA
VI = VCC or GND Outputs disabled
250
250
250
A
ICC#
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
mA
Ci
Control inputs
VI = 2.5 V or 0.5 V
7
pF
Cio
A or B ports
VO = 2.5 V or 0.5 V
12
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
All typical values are at VCC = 5 V.
The parameters IOZH and IOZL include the input leakage current.
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT646A
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
fclock
Clock frequency
0
125
0
125
MHz
tw
Pulse duration, CLK high or low
4
4
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
3
3.5
ns
th
Hold time, A or B after CLKAB
or CLKBA
1.5
1.5
ns
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT646A
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
fclock
Clock frequency
0
125
0
125
MHz
tw
Pulse duration, CLK high or low
4
4
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
3
3
ns
th
Hold time, A or B after CLKAB
or CLKBA
0
0
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT646A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
TYP
MAX
fmax
125
125
MHz
tPLH
CLKBA or CLKAB
A or B
2.2
4
5.1
2.2
6.7
ns
tPHL
CLKBA or CLKAB
A or B
1.7
4
5.1
1.2
6.7
ns
tPLH
A or B
B or A
1.5
3
4.3
1.5
5
ns
tPHL
A or B
B or A
1.5
3.3
4.6
1.5
5.6
ns
tPLH
SAB or SBA
B or A
1.5
4
5.7
1.5
7.8
ns
tPHL
SAB or SBA
B or A
1.5
3.6
4.9
1.5
6.2
ns
tPZH
OE
A or B
1.5
4.3
5.3
1.5
7
ns
tPZL
OE
A or B
3
5.8
8
3
10.5
ns
tPHZ
OE
A or B
1.5
3.5
5.8
1
7.3
ns
tPLZ
OE
A or B
1.5
3
4
1.5
5.7
ns
tPZH
DIR
A or B
1.5
4.5
5.7
1.5
7.3
ns
tPZL
DIR
A or B
2.5
6.5
9
2.5
11
ns
tPHZ
DIR
A or B
1.5
3.8
6.5
1
9
ns
tPLZ
DIR
A or B
1.5
3.8
4.7
1.2
6.7
ns
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT646A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
TYP
MAX
fmax
125
125
MHz
tPLH
CLKBA or CLKAB
A or B
2.2
4
5.1
2.2
5.6
ns
tPHL
CLKBA or CLKAB
A or B
1.7
4
5.1
1.7
5.6
ns
tPLH
A or B
B or A
1.5
3
4.3
1.5
4.8
ns
tPHL
A or B
B or A
1.5
3.3
4.6
1.5
5.4
ns
tPLH
SAB or SBA
B or A
1.5
4
5.1
1.5
6.5
ns
tPHL
SAB or SBA
B or A
1.5
3.6
4.9
1.5
5.9
ns
tPZH
OE
A or B
1.5
4.3
5.3
1.5
6.3
ns
tPZL
OE
A or B
3
5.8
7.4
3
8.8
ns
tPHZ
OE
A or B
1.5
3.5
4.5
1.5
5
ns
tPLZ
OE
A or B
1.5
3
4
1.5
4.5
ns
tPZH
DIR
A or B
1.5
4.5
5.7
1.5
6.7
ns
tPZL
DIR
A or B
2.5
6.5
9
2.5
9.5
ns
tPHZ
DIR
A or B
1.5
3.8
5
1.5
5.7
ns
tPLZ
DIR
A or B
1.5
3.8
4.7
1.5
6
ns
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G JULY 1991 REVISED MAY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
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