SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
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SMJ: QML Processing to MILPRF38535
D
SM: Standard Processing
D
TMP: Commercial Level Processing TAB
D
Operating Temperature Ranges:
Military (M) 55
C to 125
C
Special (S) 55
C to 100
C
Commercial (C) 25
C to 85
C
Commercial (L) 0
C to 70
C
D
Highest Performance Floating-Point Digital
Signal Processor (DSP)
C40-60:
33-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS,
384 MBps
C40-50:
40-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS,
320 MBps
C40-40:
50-ns Instruction Cycle Time:
40 MFLOPS, 20 MIPS, 220 MOPS,
256 MBps
D
Six Communications Ports
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6-Channel Direct Memory Access (DMA)
Coprocessor
D
Single-Cycle Conversion to and From
IEEE-745 Floating-Point Format
D
Single Cycle 1/x, 1/
D
Source-Code Compatible With SMJ320C30
D
Validated Ada Compiler
D
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
D
12 40-Bit Registers, 8 Auxiliary Registers,
14 Control Registers, and 2 Timers
D
IEEE Standard 1149.1
Test-Access Port
(JTAG)
D
Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
High Port-Data Rate of 100 MBytes/s
(Each Bus)
16G-Byte Continuous
Program/Data/Peripheral Address Space
Memory-Access Request for Fast,
Intelligent Bus Arbitration
Separate Address-, Data-, and
Control-Enable Pins
Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
D
Packaging:
325-Pin Ceramic Grid Array (GF Suffix)
352-Lead Ceramic Quad Flatpack
(HFH Suffix)
324-Pad JEDEC-Standard TAB Frame
D
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC
) Technology by
Texas Instruments (TI
)
D
Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
D
On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
512-Byte Instruction Cache
8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories Over Any One of the
Communications Ports
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
x
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
EPIC and TI are trademarks of Texas Instruments Incorporated.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pinouts
352-LEAD HFH QUAD FLATPACK PACKAGE
(TOP VIEW)
352
265
264
177
176
89
88
1
1
2
3
4
5
6
7
8
9
10
11 13
12
15
14 16
17
18
19
20
21
22
23
24
25
26 28
27
30
29 31
32
33
34
35
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
Pin A1
325-PIN GF GRID ARRAY PACKAGE
(BOTTOM VIEW)
1
TAB 325-LEAD OLB/ILB
TAPE AUTOMATED BONDING (TAB) PACKAGE
(TOP VIEW)
See the pin assignments tables and the signal description table for location and description of all pins.
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description
The C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-
m,
double-level metal CMOS technology. The 320C40 is a part of the fourth-generation DSPs from Texas
Instruments and is designed primarily for parallel processing.
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
operation
The 320C40 has six on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity to other C4x processors with no
external-glue logic. The communication ports remove input/output bottlenecks, and the independent smart
DMA coprocessor is able to handle the CPU input/output burden.
central processing unit
The 320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:
D
Eight operations/cycle:
40/32-bit floating-point/integer multiply
40/32-bit floating-point/integer arithmetic logic unit (ALU) operation
Two data accesses
Two address-register updates
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IEEE floating-point conversion
D
Divide and square-root support
D
C3x assembly language compatibility
D
Byte and halfword accessibility
DMA coprocessor
The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.
The key features of the DMA processor are:
D
Link pointers that allow DMA channels to autoinitialize without CPU intervention
D
Parallel CPU operation and DMA transfers
D
Six DMA channels that support memory-to-memory data transfers
D
Split-mode operation doubles the available DMA channels to 12 when data transfers to and from a
communication port are required.
communication ports
The C40 is the first DSP with on-chip communication ports for processor-to-processor communication with no
external hardware and simple communication software. The features of the communication ports are:
D
Direct interprocessor communication and processor I/O
D
Six communication ports for direct interprocessor communication and processor I/O
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20M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
communication ports
(continued)
D
Separate 8-word-deep input and output FIFO buffers for processor-to-processor communication and I/O
D
Automatic arbitration and handshaking for direct processor-to-processor connection
communication-port software reset (C40 silicon revision
5.0)
The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port software-reset address as specified in Table 1. This feature is not present in
C40 silicon revision < 5.0. This software reset flushes any word or byte already present in the FIFOs but it does
not affect the status of the communication-port pins. Figure 1 shows an example of
communication-port-software reset.
Table 1. Communication-Port Software-Reset Address
0
0x0100043
1
0x0100053
2
0x0100063
3
0x0100073
4
0x0100083
5
0x0100093
; -;
; RESET1:Flush's FIFO data for communication port 1;
; -;
RESET1 push
AR0
; Save registers
push
R0
;
push
RC
;
ldhi
010h,AR0
; Set AR0 to base address of COM 1
or
050h,AR0
;
flush: rpts
1
; Flush FIFO data with back-to-back write
sti
R0,*+AR0(3)
;
rpts
10
; Wait
nop
;
ldi
*+AR0(0),R0
; Check for new data from other port
and
01FE0h,R0
;
bnz
flush
;
pop
RC
; Restore registers
pop
R0
;
pop
AR0
;
rets
; Return
Figure 1. Example of Communication-Port-Software Reset
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
NMI with bus-grant feature (C40 silicon revision
5.0)
The 320C40 devices have a software-configurable feature that forces the internal-peripheral bus to ready when
the NMI signal is asserted. This feature is not present in C40 silicon revision < 5.0. The NMI bus-grant feature
is enabled when bits 1918 of the status register (ST) are set to 10b. When enabled, a peripheral bus-grant
signal is generated on the falling edge of NMI. When NMI is asserted and this feature is not enabled, the CPU
stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing to a full FIFO or
reading an empty FIFO. This feature is useful in correcting communication-port errors when used in conjunction
with the communication-port software-reset feature.
IDLE2 clock-stop power-down mode (C40 silicon revision
5.0)
The 320C40 has a clock-stop mode or power-down mode (IDLE2) to achieve extremely low power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 being held high. To exit
IDLE2, assert one of the IIOF3IIOF0 pins configured as an external interrupt instead of a general-purpose I/O.
A macro showing how to generate the IDLE2 opcode is given in Figure 2. During this power-down mode:
D
No instructions are executed
D
The CPU, peripherals, and internal memory retain their previous state.
D
The external-bus outputs are idle. The address lines remain in their previous state, the data lines are in
the high-impedance state, and the output-control signals are inactive.
; --;
; IDLE2: Macro to generate idle2 opcode ;
; -;
IDLE2
.macro
.word
06000001h
.endm
Figure 2. Example of Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180
out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after execution of a return opcode.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.
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