SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
D
Full Parallel Access for Loading
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54BCT574 . . . J OR W PACKAGE
SN74BCT574 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
1Q
8D
GND
CLK
V
CC
SN54BCT574 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the 'BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74BCT574N
SN74BCT574N
SOIC
DW
Tube
SN74BCT574DW
BCT574
0
C to 70
C
SOIC DW
Tape and reel
SN74BCT574DWR
BCT574
SOP NS
Tape and reel
SN74BCT574NSR
BCT574
SSOP DB
Tape and reel
SN74BCT574DBR
BT574
CDIP J
Tube
SNJ54BCT574J
SNJ54BCT574J
55
C to 125
C
CFP W
Tube
SNJ54BCT574W
SNJ54BCT574W
LCCC FK
Tube
SNJ54BCT574FK
SNJ54BCT574FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
Q
L
H
H
L
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
CLK
1D
1Q
1
11
2
19
To Seven Other Channels
1D
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state: SN54BCT574
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74BCT574 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54BCT574
SN74BCT574
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High-level output current
12
15
mA
IOL
Low-level output current
48
64
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54BCT574
SN74BCT574
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
IOH = 3 mA
2.4
3.3
2.4
3.3
VOH
VCC = 4.5 V
IOH = 12 mA
2
3.2
V
IOH = 15 mA
2
3.1
VOL
VCC = 4 5 V
IOL = 48 mA
0.38
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.42
0.55
V
II
VCC = 5.5 V,
VI = 5.5 V
0.4
0.4
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.5 V
0.6
0.6
mA
IOS
VCC = 5.5 V,
VO = 0
100
225
100
225
mA
IOZH
VCC = 5.5 V,
VO = 2.7 V
50
50
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
50
50
A
ICCL
VCC = 5.5 V,
Outputs open
38.1
62
38.1
62
mA
ICCH
VCC = 5.5 V,
Outputs open
4.9
8
4.9
8
mA
ICCZ
VCC = 5.5 V,
Outputs open
4.5
8
4.9
8
mA
Ci
VCC = 5 V,
VI = 2.5 V or 0.5 V
5.5
pF
Co
VCC = 5 V,
VO = 2.5 V or 0.5 V
7.5
pF
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
C
SN54BCT574
SN74BCT574
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
77
77
77
MHz
tw
Pulse duration, CLK high or low
6.5
6.5
6.5
ns
t
Setup time data before CLK
High
4.5
4.5
4.5
ns
tsu
Setup time, data before CLK
Low
6
6
6
ns
th
Hold time, data after CLK
High or low
0
1
0
ns
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54BCT574
SN74BCT574
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
77
77
77
MHz
tPLH
CLK
Q
2.2
6.5
8.6
2.2
11.2
2.2
10
ns
tPHL
CLK
Q
2.8
6.1
8
2.8
9.7
2.8
8.9
ns
tPZH
OE
Q
2.5
6.4
8.1
2.5
10.9
2.5
10.4
ns
tPZL
OE
Q
3.7
7.3
9.2
3.7
11.3
3.7
10.9
ns
tPHZ
OE
Q
1
4.4
7.4
1
8
1
7.5
ns
tPLZ
OE
Q
1.3
4.2
5.8
1.3
7.1
1.3
6.4
ns
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, tr = tf
2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
Test
Point
R1
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
CL
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
(see Note B)
Data Input
(see Note B)
1.5 V
1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
(see Note B)
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
tPHL
tPLH
tPLH
tPHL
Input
(see Note B)
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Notes C and D)
Waveform 2
(see Notes C and D)
0 V
VOH
VOL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Figure 1. Load Circuit and Voltage Waveforms
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