SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A FEBRUARY 1991 REVISED JULY 1994
Copyright
1994, Texas Instruments Incorporated
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
C
High-Drive Outputs ( 32-mA I
OH
,
64-mA I
OL
)
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
description
The
ABT533 are 8-bit transparent D-type latches
with 3-state outputs designed specifically for
driving highly capacitive or relatively low-
impedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
When the latch-enable (LE) input is high, the
Q outputs follow the complements of the data
(D) inputs. When LE is taken low, the Q outputs
are latched at the inverse of the levels set up at the
D inputs. The
ABT533 provides inverted data at
its outputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT533 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT533 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74ABT533 is characterized for operation from 40
C to 85
C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54ABT533 . . . J PACKAGE
SN74ABT533 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54ABT533 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
5Q
5D
8Q
4Q
GND
LE
V
CC
EPIC-
B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A FEBRUARY 1991 REVISED JULY 1994
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
L
L
H
L
H
L
L
X
Q0
H
X
X
Z
logic symbol
logic diagram (positive logic)
1D
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
2
5
6
9
12
15
16
19
EN
1
C1
11
LE
OE
1Q
2Q
3Q
4Q
5Q
6Q
8Q
7Q
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
1D
C1
C1
C1
C1
C1
C1
C1
C1
1D
1D
1D
1D
1D
1D
1D
OE
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1
1
11
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A FEBRUARY 1991 REVISED JULY 1994
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT533
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT533
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): DB package
0.6 W
. . . . . . . . . . . . . . . . . . . .
DW package
1.6 W
. . . . . . . . . . . . . . . . . . .
N package
1.3 W
. . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT533
SN74ABT533
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t /
v
Input transition rise or fall rate
10
10
ns / V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A FEBRUARY 1991 REVISED JULY 1994
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT533
SN74ABT533
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
II
VCC = 5.5 V,
VI = VCC or GND
1
1
1
A
IOZH
VCC = 5.5 V,
VO = 2.7 V
10
10
10
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
10
10
10
A
Ioff
VCC = 0,
VI or VO
4.5 V
150
150
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
140
180
50
180
50
180
mA
V
5 5 V
I
0
Outputs high
1
250
250
250
A
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs low
24
30
30
30
mA
VI = VCC or GND
Outputs disabled
0.5
250
250
250
A
VCC = 5.5 V,
Outputs enabled
1.5
1.5
1.5
ICC
VCC 5.5 V,
One input at 3.4 V,
Outputs disabled
1.5
1.5
1.5
mA
CC
Other inputs at VCC or GND
Control inputs
1.5
1.5
1.5
Ci
VI = 2.5 V or 0.5 V
3
pF
Co
VO = 2.5 V or 0.5 V
9
pF
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
All typical values are at VCC = 5 V.
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure1)
VCC = 5 V,
TA = 25
C
SN54ABT533
SN74ABT533
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tw
Pulse duration, LE high
3.3
3.3
3.3
ns
tsu
Setup time, data before LE
High or low
2.1
2.1
2.1
ns
th
Hold time, data after LE
High or low
1.5
1.5
1.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A FEBRUARY 1991 REVISED JULY 1994
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54ABT533
SN74ABT533
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPLH
D
Q
1.9
4.2
5.4
1.9
6.7
1.9
6.4
ns
tPHL
D
Q
3.1
4.9
6.3
3.1
6.9
3.1
6.6
ns
tPLH
LE
Q
2.7
4.9
6.2
2.7
7.6
2.7
7.3
ns
tPHL
LE
Q
3.5
5.4
6.8
3.5
7.5
3.5
7.3
ns
tPZH
OE
Q
1.6
3.7
4.8
1.6
5.8
1.6
5.7
ns
tPZL
OE
Q
2.4
4.2
6.2
2.4
6.9
2.4
6.7
ns
tPHZ
OE
Q
2.8
5.1
6.2
2.8
7.2
2.8
6.9
ns
tPLZ
OE
Q
2
4.1
6
2
6.9
2
6.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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