SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25
C
D
High-Drive Outputs (32-mA I
OH
, 64-mA I
OL
)
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
SN54ABT125 . . . J OR W PACKAGE
SN74ABT125 . . . D, DB, N, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
SN54ABT125 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
SN74ABT125 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1OE
3Y
V
GND
CC
description/ordering information
The 'ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74ABT125N
SN74ABT125N
QFN RGY
Tape and reel
SN74ABT125RGYR
AB125
SOIC
D
Tube
SN74ABT125D
ABT125
40
C to 85
C
SOIC D
Tape and reel
SN74ABT125DR
ABT125
SOP NS
Tape and reel
SN74ABT125NSR
ABT125
SSOP DB
Tape and reel
SN74ABT125DBR
AB125
TSSOP PW
Tape and reel
SN74ABT125PWR
AB125
CDIP J
Tube
SNJ54ABT125J
SNJ54ABT125J
55
C to 125
C
CFP W
Tube
SNJ54ABT125W
SNJ54ABT125W
LCCC FK
Tube
SNJ54ABT125FK
SNJ54ABT125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
1
1OE
2
1A
1Y
3
4
2OE
5
2A
2Y
6
10
3OE
9
3A
3Y
8
13
4OE
12
4A
4Y
11
Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT125 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT125 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package
47
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54ABT125
SN74ABT125
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT125
SN74ABT125
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
1.2
V
VCC = 4.5 V,
IOH = 3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = 3 mA
3
3
3
V
VOH
VCC = 4 5 V
IOH = 24 mA
2
2
V
VCC = 4.5 V
IOH = 32 mA
2*
2
VOL
VCC = 4 5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
VCC = 0 to 5.5 V,
VI = VCC or GND
1
1
1
A
IOZPU
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
50
50
50
A
IOZPD
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
50
50
50
A
IOZH
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
2 V
10
10
10
A
IOZL
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
2 V
10
10
10
A
Ioff
VCC = 0,
VI or VO
4.5 V
100
100
A
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
50
100
200
50
200
50
200
mA
VCC = 5.5 V,
Outputs high
1
250
250
250
A
ICC
VCC = 5.5 V,
IO = 0,
Outputs low
24
30
30
30
mA
VI = VCC or GND
Outputs disabled
0.5
250
250
250
A
Data
VCC = 5.5 V,
One input at 3.4 V,
Outputs enabled
1.5
1.5
1.5
ICC
inputs
,
Other inputs at
VCC or GND
Outputs disabled
0.05
0.05
0.05
mA
Control
inputs
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1.5
1.5
1.5
Ci
VI = 2.5 V or 0.5 V
3
pF
Co
VO = 2.5 V or 0.5 V
7
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
All typical values are at VCC = 5 V.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This limit may vary among suppliers.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54ABT125
SN74ABT125
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPLH
A
Y
1
3.2
4.6
1
6
1
4.9
ns
tPHL
A
Y
1
2.5
4.6
1
6.2
1
4.9
ns
tPZH
OE
Y
1
3.6
5
1
6
1
5.9
ns
tPZL
OE
Y
1
2.5
6.2
1
7.5
1
6.8
ns
tPHZ
OE
Y
1
3.8
5.4
1
6.3
1
6.2
ns
tPLZ
OE
Y
1
3.3
5.3
1
6.5
1
6.2
ns
This limit may vary among suppliers.
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